derek.holloway
7502bf64a4
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271 lines
8.1 KiB
LLVM
271 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple armv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LE
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; RUN: llc < %s -mtriple armebv7-eabi -o - | FileCheck %s --check-prefixes=CHECK,CHECK-BE
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define arm_aapcs_vfpcc <8 x i8> @vmov_i8() {
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; CHECK-LE-LABEL: vmov_i8:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i8:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000000000
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; CHECK-BE-NEXT: vrev64.8 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1>
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}
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define arm_aapcs_vfpcc <4 x i16> @vmov_i16_a() {
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; CHECK-LE-LABEL: vmov_i16_a:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xffff000000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i16_a:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xffff000000000000
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; CHECK-BE-NEXT: vrev64.16 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 -1>
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}
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define arm_aapcs_vfpcc <4 x i16> @vmov_i16_b() {
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; CHECK-LE-LABEL: vmov_i16_b:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i16_b:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff000000000000
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; CHECK-BE-NEXT: vrev64.16 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 255>
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}
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define arm_aapcs_vfpcc <4 x i16> @vmov_i16_c() {
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; CHECK-LE-LABEL: vmov_i16_c:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i16_c:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000000000
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; CHECK-BE-NEXT: vrev64.16 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 65280>
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}
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_a() {
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; CHECK-LE-LABEL: vmov_i32_a:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xffffffff00000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i32_a:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xffffffff00000000
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; CHECK-BE-NEXT: vrev64.32 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <2 x i32> <i32 0, i32 -1>
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}
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_b() {
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; CHECK-LE-LABEL: vmov_i32_b:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i32_b:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000
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; CHECK-BE-NEXT: vrev64.32 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <2 x i32> <i32 0, i32 255>
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}
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_c() {
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; CHECK-LE-LABEL: vmov_i32_c:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff0000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i32_c:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000000000
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; CHECK-BE-NEXT: vrev64.32 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <2 x i32> <i32 0, i32 65280>
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}
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_d() {
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; CHECK-LE-LABEL: vmov_i32_d:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff000000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i32_d:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff000000000000
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; CHECK-BE-NEXT: vrev64.32 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <2 x i32> <i32 0, i32 16711680>
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}
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define arm_aapcs_vfpcc <2 x i32> @vmov_i32_e() {
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; CHECK-LE-LABEL: vmov_i32_e:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xff00000000000000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i32_e:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff00000000000000
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; CHECK-BE-NEXT: vrev64.32 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <2 x i32> <i32 0, i32 4278190080>
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}
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define arm_aapcs_vfpcc <1 x i64> @vmov_i64_a() {
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; CHECK-LABEL: vmov_i64_a:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i8 d0, #0xff
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; CHECK-NEXT: bx lr
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ret <1 x i64> <i64 -1>
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}
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define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
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; CHECK-LE-LABEL: vmov_i64_b:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 d0, #0xffff00ff0000ff
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_i64_b:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000ff00ffff00
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; CHECK-BE-NEXT: vrev64.32 d0, d16
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; CHECK-BE-NEXT: bx lr
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ret <1 x i64> <i64 72056498804490495>
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}
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define arm_aapcs_vfpcc <2 x i64> @vmov_v2i64_b() {
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; CHECK-LABEL: vmov_v2i64_b:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vmov.i64 q0, #0xffff00ff0000ff
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; CHECK-NEXT: bx lr
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ret <2 x i64> <i64 72056498804490495, i64 72056498804490495>
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}
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define arm_aapcs_vfpcc <4 x i32> @vmov_v4i32_b() {
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; CHECK-LE-LABEL: vmov_v4i32_b:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 q0, #0xff0000ff00ffff00
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmov_v4i32_b:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 q0, #0xffff00ff0000ff
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; CHECK-BE-NEXT: bx lr
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ret <4 x i32> <i32 u0xffff00, i32 u0xff0000ff, i32 u0xffff00, i32 u0xff0000ff>
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}
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define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {
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; CHECK-LE-LABEL: and_v2i64_b:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 q8, #0xffff00ff0000ff
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; CHECK-LE-NEXT: vand q0, q0, q8
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: and_v2i64_b:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
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; CHECK-BE-NEXT: vrev64.32 q8, q8
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; CHECK-BE-NEXT: vand q0, q0, q8
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; CHECK-BE-NEXT: bx lr
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%b = and <2 x i64> %a, <i64 72056498804490495, i64 72056498804490495>
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ret <2 x i64> %b
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}
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define arm_aapcs_vfpcc <4 x i32> @and_v4i32_b(<4 x i32> %a) {
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; CHECK-LE-LABEL: and_v4i32_b:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
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; CHECK-LE-NEXT: vand q0, q0, q8
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: and_v4i32_b:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
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; CHECK-BE-NEXT: vrev64.32 q9, q0
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; CHECK-BE-NEXT: vand q8, q9, q8
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; CHECK-BE-NEXT: vrev64.32 q0, q8
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; CHECK-BE-NEXT: bx lr
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%b = and <4 x i32> %a, <i32 u0xffff00, i32 u0xff0000ff, i32 u0xffff00, i32 u0xff0000ff>
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ret <4 x i32> %b
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}
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define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {
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; CHECK-LE-LABEL: vmvn_v16i8_m1:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmvn.i32 q0, #0x10000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: vmvn_v16i8_m1:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmvn.i32 q0, #0x1
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; CHECK-BE-NEXT: bx lr
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ret <8 x i16> <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
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}
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define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
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; CHECK-LE-LABEL: and_v8i16_m1:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vbic.i32 q0, #0x10000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: and_v8i16_m1:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vrev64.16 q8, q0
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; CHECK-BE-NEXT: vbic.i32 q8, #0x10000
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; CHECK-BE-NEXT: vrev64.16 q0, q8
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; CHECK-BE-NEXT: bx lr
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%b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
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ret <8 x i16> %b
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}
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define arm_aapcs_vfpcc <8 x i16> @or_v8i16_1(<8 x i16> %a) {
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; CHECK-LE-LABEL: or_v8i16_1:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vorr.i32 q0, #0x10000
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: or_v8i16_1:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vrev64.16 q8, q0
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; CHECK-BE-NEXT: vorr.i32 q8, #0x10000
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; CHECK-BE-NEXT: vrev64.16 q0, q8
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; CHECK-BE-NEXT: bx lr
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%b = or <8 x i16> %a, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
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ret <8 x i16> %b
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}
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define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_m1(<8 x i16> %a) {
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; CHECK-LE-LABEL: xor_v8i16_m1:
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; CHECK-LE: @ %bb.0:
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; CHECK-LE-NEXT: vmvn.i32 q8, #0x10000
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; CHECK-LE-NEXT: veor q0, q0, q8
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: xor_v8i16_m1:
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; CHECK-BE: @ %bb.0:
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; CHECK-BE-NEXT: vmvn.i32 q8, #0x10000
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; CHECK-BE-NEXT: vrev64.16 q9, q0
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; CHECK-BE-NEXT: veor q8, q9, q8
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; CHECK-BE-NEXT: vrev64.16 q0, q8
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; CHECK-BE-NEXT: bx lr
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%b = xor <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
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ret <8 x i16> %b
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}
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