derek.holloway
7502bf64a4
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67 lines
2.7 KiB
LLVM
67 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple armv7 -O1 | FileCheck %s -check-prefix=CHECK-LE-NORMAL
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; RUN: llc < %s -mtriple armv7 -O1 -combiner-reduce-load-op-store-width-force-narrowing-profitable=1 | FileCheck %s -check-prefix=CHECK-LE-NARROW
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; RUN: llc < %s -mtriple armv7eb -O1 | FileCheck %s -check-prefix=CHECK-BE-NORMAL
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; RUN: llc < %s -mtriple armv7eb -O1 -combiner-reduce-load-op-store-width-force-narrowing-profitable=1 | FileCheck %s -check-prefix=CHECK-BE-NARROW
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; This is a reproducer for a bug when DAGCombiner::ReduceLoadOpStoreWidth
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; would end up narrowing the load-op-store sequence into this SDNode sequence
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; for little-endian
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;
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; t18: i32,ch = load<(load (s32) from %ir.p1 + 8, align 8)> t0, t17, undef:i32
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; t20: i32 = or t18, Constant:i32<65534>
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; t21: ch = store<(store (s32) into %ir.p1 + 8, align 8)> t18:1, t20, t17, undef:i32
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;
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; This was wrong since it accesses memory above %ir.p1+9 which is outside the
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; "store size" for the original store.
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;
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; For big-endian we used to hit an assertion due to passing a negative offset
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; to getMemBasePlusOffset (at least after commit 3e1b55cafc95d4ef4, while
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; before that commit we got load/store instructions that accessed memory at a
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; negative offset from %p1).
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;
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define i16 @test(ptr %p1) {
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; CHECK-LE-NORMAL-LABEL: test:
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; CHECK-LE-NORMAL: @ %bb.0: @ %entry
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; CHECK-LE-NORMAL-NEXT: ldrh r1, [r0, #8]
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; CHECK-LE-NORMAL-NEXT: mvn r2, #1
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; CHECK-LE-NORMAL-NEXT: orr r1, r1, r2
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; CHECK-LE-NORMAL-NEXT: strh r1, [r0, #8]
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; CHECK-LE-NORMAL-NEXT: mov r0, #0
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; CHECK-LE-NORMAL-NEXT: bx lr
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;
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; CHECK-LE-NARROW-LABEL: test:
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; CHECK-LE-NARROW: @ %bb.0: @ %entry
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; CHECK-LE-NARROW-NEXT: ldr r1, [r0, #6]
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; CHECK-LE-NARROW-NEXT: orr r1, r1, #16646144
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; CHECK-LE-NARROW-NEXT: orr r1, r1, #-16777216
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; CHECK-LE-NARROW-NEXT: str r1, [r0, #6]
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; CHECK-LE-NARROW-NEXT: mov r0, #0
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; CHECK-LE-NARROW-NEXT: bx lr
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;
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; CHECK-BE-NORMAL-LABEL: test:
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; CHECK-BE-NORMAL: @ %bb.0: @ %entry
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; CHECK-BE-NORMAL-NEXT: ldrh r1, [r0]
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; CHECK-BE-NORMAL-NEXT: mvn r2, #1
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; CHECK-BE-NORMAL-NEXT: orr r1, r1, r2
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; CHECK-BE-NORMAL-NEXT: strh r1, [r0]
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; CHECK-BE-NORMAL-NEXT: mov r0, #0
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; CHECK-BE-NORMAL-NEXT: bx lr
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;
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; CHECK-BE-NARROW-LABEL: test:
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; CHECK-BE-NARROW: @ %bb.0: @ %entry
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; CHECK-BE-NARROW-NEXT: ldr r1, [r0]
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; CHECK-BE-NARROW-NEXT: orr r1, r1, #16646144
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; CHECK-BE-NARROW-NEXT: orr r1, r1, #-16777216
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; CHECK-BE-NARROW-NEXT: str r1, [r0]
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; CHECK-BE-NARROW-NEXT: mov r0, #0
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; CHECK-BE-NARROW-NEXT: bx lr
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entry:
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%load = load i80, ptr %p1, align 32
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%mask = shl i80 -1, 65
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%op = or i80 %load, %mask
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store i80 %op, ptr %p1, align 32
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ret i16 0
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}
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