derek.holloway
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42 lines
1.8 KiB
YAML
42 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s
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# Make sure the MOVCC to conditional instruction peephole doesn't change the
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# register class to one that's invalid.
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--- |
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target triple = "armv7-unknown-unknown"
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define i32 @test(i32 %x, i32 %y) {
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ret i32 undef
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}
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...
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---
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name: test
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tracksRegLiveness: true
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body: |
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bb.0 (%ir-block.0):
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liveins: $r0, $r1
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; CHECK-LABEL: name: test
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; CHECK: liveins: $r0, $r1
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; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r1
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; CHECK-NEXT: [[MOVsi:%[0-9]+]]:gpr = MOVsi [[COPY1]], 27, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: [[ORRrsi:%[0-9]+]]:gpr = ORRrsi [[MOVsi]], [[COPY1]], 234, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 155, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: [[ORRrsi1:%[0-9]+]]:gprnopc = ORRrsi killed [[MOVsi1]], killed [[MOVsi]], 106, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: [[UXTH:%[0-9]+]]:gprnopc = UXTH killed [[ORRrsi1]], 0, 0 /* CC::eq */, $cpsr, implicit [[ORRrsi]](tied-def 0)
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; CHECK-NEXT: $r0 = COPY killed [[UXTH]]
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; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gpr = COPY $r0
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%1:gpr = COPY $r1
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%2:gpr = MOVsi %1:gpr, 27, 14, $noreg, $noreg
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%3:gpr = ORRrsi %2:gpr, %1:gpr, 234, 14, $noreg, $noreg
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%4:gpr = MOVsi %1:gpr, 155, 14, $noreg, $noreg
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%5:gprnopc = ORRrsi killed %4:gpr, killed %2:gpr, 106, 14, $noreg, $noreg
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%6:gprnopc = UXTH killed %5:gprnopc, 0, 14, $noreg
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TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
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%7:gpr = MOVCCr %3:gpr, killed %6:gprnopc, 0, $cpsr
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$r0 = COPY killed %7
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BX_RET 14, $noreg, implicit $r0
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