derek.holloway
7502bf64a4
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23 lines
954 B
LLVM
23 lines
954 B
LLVM
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-R52
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52plus -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-R52
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; REQUIRES: asserts
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; source_filename = "sched-2.c"
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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define dso_local i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr {
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entry:
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%add = add nsw i32 %b, %a
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%add1 = add nsw i32 %d, %c
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%div = sdiv i32 %add, %add1
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ret i32 %div
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}
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; Cortex-R52 model describes it as dual-issue with two integer ALUs
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; It should be able to issue the two additions in the same cycle.
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; CHECK-R52: MI Scheduling
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; CHECK-R52: Cycle: 14
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; CHECK-R52: Scheduling SU(5) %5:gpr = nsw ADDrr %3:gpr, %2:gpr, 14, $noreg, $noreg
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; CHECK-R52: Scheduling SU(4) %4:gpr = nsw ADDrr %1:gpr, %0:gpr, 14, $noreg, $noreg
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; CHECK-R52: Cycle: 15
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