derek.holloway
7502bf64a4
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177 lines
4.3 KiB
LLVM
177 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=thumbv8 %s -o - | FileCheck %s --check-prefixes=CHECK,T2
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; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefixes=CHECK,T2
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; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s --check-prefixes=CHECK,T1
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; RUN: llc -mtriple=thumbv7em %s -o - | FileCheck %s --check-prefixes=CHECK,T2
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; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefixes=V6M
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; Armv6m targets don't have a sdiv instruction, so sdiv should not appear at
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; all in the output:
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; V6M: .file {{.*}}
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; V6M-NOT: sdiv
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; V6M-NOT: idiv
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; Test sdiv i16
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define dso_local signext i16 @f0(i16 signext %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f0:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #2
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; CHECK-NEXT: sdiv r0, r0, r1
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; CHECK-NEXT: sxth r0, r0
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; CHECK-NEXT: bx lr
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;
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; V6M-LABEL: f0:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: uxth r1, r0
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; V6M-NEXT: lsrs r1, r1, #15
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; V6M-NEXT: adds r0, r0, r1
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; V6M-NEXT: sxth r0, r0
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; V6M-NEXT: asrs r0, r0, #1
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; V6M-NEXT: bx lr
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entry:
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%0 = sdiv i16 %F, 2
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ret i16 %0
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}
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; Same as above, but now with i32
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define dso_local i32 @f1(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #4
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; CHECK-NEXT: sdiv r0, r0, r1
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; CHECK-NEXT: bx lr
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;
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; V6M-LABEL: f1:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: asrs r1, r0, #31
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; V6M-NEXT: lsrs r1, r1, #30
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; V6M-NEXT: adds r0, r0, r1
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; V6M-NEXT: asrs r0, r0, #2
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; V6M-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 4
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ret i32 %div
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}
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; The immediate is not a power of 2, so we expect a sdiv.
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define dso_local i32 @f2(i32 %F) local_unnamed_addr #0 {
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; CHECK-LABEL: f2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: sdiv r0, r0, r1
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; CHECK-NEXT: bx lr
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;
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; V6M-LABEL: f2:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: push {r7, lr}
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; V6M-NEXT: movs r1, #5
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; V6M-NEXT: bl __divsi3
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; V6M-NEXT: pop {r7, pc}
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entry:
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%div = sdiv i32 %F, 5
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ret i32 %div
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}
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; Try a larger power of 2 immediate: immediates larger than
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; 128 don't give any code size savings.
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define dso_local i32 @f3(i32 %F) local_unnamed_addr #0 {
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; T2-LABEL: f3:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: asrs r1, r0, #31
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; T2-NEXT: add.w r0, r0, r1, lsr #24
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; T2-NEXT: asrs r0, r0, #8
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; T2-NEXT: bx lr
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;
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; T1-LABEL: f3:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: asrs r1, r0, #31
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; T1-NEXT: lsrs r1, r1, #24
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; T1-NEXT: adds r0, r0, r1
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; T1-NEXT: asrs r0, r0, #8
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; T1-NEXT: bx lr
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;
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; V6M-LABEL: f3:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: asrs r1, r0, #31
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; V6M-NEXT: lsrs r1, r1, #24
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; V6M-NEXT: adds r0, r0, r1
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; V6M-NEXT: asrs r0, r0, #8
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; V6M-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 256
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ret i32 %div
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}
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attributes #0 = { minsize norecurse nounwind optsize readnone }
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; These functions don't have the minsize attribute set, so should not lower
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; the sdiv to sdiv, but to the faster instruction sequence.
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define dso_local signext i16 @f4(i16 signext %F) {
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; T2-LABEL: f4:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: uxth r1, r0
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; T2-NEXT: add.w r0, r0, r1, lsr #15
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; T2-NEXT: sxth r0, r0
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; T2-NEXT: asrs r0, r0, #1
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; T2-NEXT: bx lr
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;
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; T1-LABEL: f4:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: uxth r1, r0
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; T1-NEXT: lsrs r1, r1, #15
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; T1-NEXT: adds r0, r0, r1
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; T1-NEXT: sxth r0, r0
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; T1-NEXT: asrs r0, r0, #1
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; T1-NEXT: bx lr
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;
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; V6M-LABEL: f4:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: uxth r1, r0
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; V6M-NEXT: lsrs r1, r1, #15
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; V6M-NEXT: adds r0, r0, r1
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; V6M-NEXT: sxth r0, r0
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; V6M-NEXT: asrs r0, r0, #1
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; V6M-NEXT: bx lr
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entry:
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%0 = sdiv i16 %F, 2
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ret i16 %0
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}
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define dso_local i32 @f5(i32 %F) {
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; T2-LABEL: f5:
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; T2: @ %bb.0: @ %entry
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; T2-NEXT: asrs r1, r0, #31
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; T2-NEXT: add.w r0, r0, r1, lsr #30
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; T2-NEXT: asrs r0, r0, #2
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; T2-NEXT: bx lr
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;
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; T1-LABEL: f5:
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; T1: @ %bb.0: @ %entry
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; T1-NEXT: asrs r1, r0, #31
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; T1-NEXT: lsrs r1, r1, #30
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; T1-NEXT: adds r0, r0, r1
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; T1-NEXT: asrs r0, r0, #2
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; T1-NEXT: bx lr
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;
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; V6M-LABEL: f5:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: asrs r1, r0, #31
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; V6M-NEXT: lsrs r1, r1, #30
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; V6M-NEXT: adds r0, r0, r1
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; V6M-NEXT: asrs r0, r0, #2
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; V6M-NEXT: bx lr
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entry:
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%div = sdiv i32 %F, 4
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ret i32 %div
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}
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