derek.holloway
7502bf64a4
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160 lines
6.0 KiB
LLVM
160 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple armv7-- -mattr=+vfp4 -O0 -o - %s | FileCheck %s
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; RUN: llc -mtriple armv7-- -mattr=+vfp4 -O3 -o - %s | FileCheck %s --check-prefix=CHECK-O3
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declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
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declare float @llvm.experimental.constrained.sitofp.f32.i16(i16, metadata, metadata)
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declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
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declare float @llvm.experimental.constrained.uitofp.f32.i16(i16, metadata, metadata)
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define i32 @test(i32 %a, i16 %b) #0 {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: sxth r0, r1
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; CHECK-NEXT: movw r1, #0
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; CHECK-NEXT: movt r1, #17200
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; CHECK-NEXT: str r1, [sp, #4]
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; CHECK-NEXT: eor r2, r2, #-2147483648
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; CHECK-NEXT: str r2, [sp]
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; CHECK-NEXT: vldr d16, [sp]
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; CHECK-NEXT: vldr d17, .LCPI0_0
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; CHECK-NEXT: vsub.f64 d16, d16, d17
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; CHECK-NEXT: vcvt.f32.f64 s0, d16
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; CHECK-NEXT: str r1, [sp, #12]
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; CHECK-NEXT: eor r0, r0, #-2147483648
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; CHECK-NEXT: str r0, [sp, #8]
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; CHECK-NEXT: vldr d16, [sp, #8]
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; CHECK-NEXT: vsub.f64 d16, d16, d17
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; CHECK-NEXT: vcvt.f32.f64 s2, d16
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; CHECK-NEXT: vcmp.f32 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: movweq r0, #1
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 2147483648 @ double 4503601774854144
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; CHECK-NEXT: .long 1127219200
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;
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; CHECK-O3-LABEL: test:
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; CHECK-O3: @ %bb.0: @ %entry
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; CHECK-O3-NEXT: sub sp, sp, #16
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; CHECK-O3-NEXT: sxth r1, r1
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; CHECK-O3-NEXT: movw r2, #0
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; CHECK-O3-NEXT: movt r2, #17200
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; CHECK-O3-NEXT: str r2, [sp, #4]
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; CHECK-O3-NEXT: eor r0, r0, #-2147483648
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; CHECK-O3-NEXT: str r0, [sp]
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; CHECK-O3-NEXT: vldr d16, [sp]
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; CHECK-O3-NEXT: vldr d17, .LCPI0_0
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; CHECK-O3-NEXT: vsub.f64 d16, d16, d17
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; CHECK-O3-NEXT: vcvt.f32.f64 s0, d16
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; CHECK-O3-NEXT: str r2, [sp, #12]
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; CHECK-O3-NEXT: eor r0, r1, #-2147483648
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; CHECK-O3-NEXT: str r0, [sp, #8]
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; CHECK-O3-NEXT: vldr d16, [sp, #8]
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; CHECK-O3-NEXT: vsub.f64 d16, d16, d17
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; CHECK-O3-NEXT: vcvt.f32.f64 s2, d16
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; CHECK-O3-NEXT: vcmp.f32 s0, s2
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; CHECK-O3-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-O3-NEXT: mov r0, #0
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; CHECK-O3-NEXT: movweq r0, #1
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; CHECK-O3-NEXT: add sp, sp, #16
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; CHECK-O3-NEXT: bx lr
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; CHECK-O3-NEXT: .p2align 3
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; CHECK-O3-NEXT: @ %bb.1:
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; CHECK-O3-NEXT: .LCPI0_0:
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; CHECK-O3-NEXT: .long 2147483648 @ double 4503601774854144
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; CHECK-O3-NEXT: .long 1127219200
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entry:
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%conv = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #1
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%conv1 = call float @llvm.experimental.constrained.sitofp.f32.i16(i16 %b, metadata !"round.tonearest", metadata !"fpexcept.strict") #1
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%cmp = call i1 @llvm.experimental.constrained.fcmp.f32(float %conv, float %conv1, metadata !"oeq", metadata !"fpexcept.strict") #1
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @test2(i32 %a, i16 %b) #0 {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: mov r2, r0
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; CHECK-NEXT: uxth r0, r1
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; CHECK-NEXT: movw r1, #0
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; CHECK-NEXT: movt r1, #17200
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; CHECK-NEXT: str r1, [sp, #4]
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; CHECK-NEXT: eor r2, r2, #-2147483648
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; CHECK-NEXT: str r2, [sp]
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; CHECK-NEXT: vldr d16, [sp]
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; CHECK-NEXT: vldr d17, .LCPI1_0
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; CHECK-NEXT: vsub.f64 d16, d16, d17
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; CHECK-NEXT: vcvt.f32.f64 s0, d16
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; CHECK-NEXT: str r1, [sp, #12]
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; CHECK-NEXT: str r0, [sp, #8]
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; CHECK-NEXT: vldr d16, [sp, #8]
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; CHECK-NEXT: vldr d17, .LCPI1_1
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; CHECK-NEXT: vsub.f64 d16, d16, d17
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; CHECK-NEXT: vcvt.f32.f64 s2, d16
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; CHECK-NEXT: vcmp.f32 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: movweq r0, #1
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 2147483648 @ double 4503601774854144
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; CHECK-NEXT: .long 1127219200
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; CHECK-NEXT: .LCPI1_1:
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; CHECK-NEXT: .long 0 @ double 4503599627370496
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; CHECK-NEXT: .long 1127219200
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;
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; CHECK-O3-LABEL: test2:
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; CHECK-O3: @ %bb.0: @ %entry
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; CHECK-O3-NEXT: sub sp, sp, #16
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; CHECK-O3-NEXT: uxth r1, r1
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; CHECK-O3-NEXT: movw r2, #0
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; CHECK-O3-NEXT: movt r2, #17200
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; CHECK-O3-NEXT: str r2, [sp, #4]
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; CHECK-O3-NEXT: eor r0, r0, #-2147483648
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; CHECK-O3-NEXT: str r0, [sp]
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; CHECK-O3-NEXT: vldr d16, [sp]
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; CHECK-O3-NEXT: vldr d17, .LCPI1_0
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; CHECK-O3-NEXT: vsub.f64 d16, d16, d17
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; CHECK-O3-NEXT: vcvt.f32.f64 s0, d16
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; CHECK-O3-NEXT: str r2, [sp, #12]
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; CHECK-O3-NEXT: str r1, [sp, #8]
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; CHECK-O3-NEXT: vldr d16, [sp, #8]
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; CHECK-O3-NEXT: vldr d17, .LCPI1_1
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; CHECK-O3-NEXT: vsub.f64 d16, d16, d17
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; CHECK-O3-NEXT: vcvt.f32.f64 s2, d16
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; CHECK-O3-NEXT: vcmp.f32 s0, s2
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; CHECK-O3-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-O3-NEXT: mov r0, #0
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; CHECK-O3-NEXT: movweq r0, #1
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; CHECK-O3-NEXT: add sp, sp, #16
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; CHECK-O3-NEXT: bx lr
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; CHECK-O3-NEXT: .p2align 3
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; CHECK-O3-NEXT: @ %bb.1:
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; CHECK-O3-NEXT: .LCPI1_0:
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; CHECK-O3-NEXT: .long 2147483648 @ double 4503601774854144
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; CHECK-O3-NEXT: .long 1127219200
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; CHECK-O3-NEXT: .LCPI1_1:
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; CHECK-O3-NEXT: .long 0 @ double 4503599627370496
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; CHECK-O3-NEXT: .long 1127219200
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entry:
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%conv = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #1
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%conv1 = call float @llvm.experimental.constrained.uitofp.f32.i16(i16 %b, metadata !"round.tonearest", metadata !"fpexcept.strict") #1
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%cmp = call i1 @llvm.experimental.constrained.fcmp.f32(float %conv, float %conv1, metadata !"oeq", metadata !"fpexcept.strict") #1
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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attributes #0 = { strictfp noinline optnone }
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attributes #1 = { strictfp }
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