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TheRock/compiler/amd-llvm/llvm/test/CodeGen/DirectX/legalize-i8-alloca.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes='dxil-legalize' -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
define void @const_i8_store() {
; CHECK-LABEL: define void @const_i8_store() {
; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4
; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4
; CHECK-NEXT: store i32 1, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0
; CHECK-NEXT: store i32 [[TMP2]], ptr [[GEP]], align 4
; CHECK-NEXT: ret void
;
%accum.i.flat = alloca [1 x i32], align 4
%i = alloca i8, align 4
store i8 1, ptr %i
%i8.load = load i8, ptr %i
%z = zext i8 %i8.load to i32
%gep = getelementptr i32, ptr %accum.i.flat, i32 0
store i32 %z, ptr %gep, align 4
ret void
}
define void @const_add_i8_store() {
; CHECK-LABEL: define void @const_add_i8_store() {
; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4
; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4
; CHECK-NEXT: store i32 4, ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0
; CHECK-NEXT: store i32 [[TMP2]], ptr [[GEP]], align 4
; CHECK-NEXT: ret void
;
%accum.i.flat = alloca [1 x i32], align 4
%i = alloca i8, align 4
%add_i8 = add nsw i8 3, 1
store i8 %add_i8, ptr %i
%i8.load = load i8, ptr %i
%z = zext i8 %i8.load to i32
%gep = getelementptr i32, ptr %accum.i.flat, i32 0
store i32 %z, ptr %gep, align 4
ret void
}
define void @var_i8_store(i1 %cmp.i8) {
; CHECK-LABEL: define void @var_i8_store(
; CHECK-SAME: i1 [[CMP_I8:%.*]]) {
; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4
; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMP_I8]], i32 1, i32 2
; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0
; CHECK-NEXT: store i32 [[TMP3]], ptr [[GEP]], align 4
; CHECK-NEXT: ret void
;
%accum.i.flat = alloca [1 x i32], align 4
%i = alloca i8, align 4
%select.i8 = select i1 %cmp.i8, i8 1, i8 2
store i8 %select.i8, ptr %i
%i8.load = load i8, ptr %i
%z = zext i8 %i8.load to i32
%gep = getelementptr i32, ptr %accum.i.flat, i32 0
store i32 %z, ptr %gep, align 4
ret void
}
define void @conflicting_cast(i1 %cmp.i8) {
; CHECK-LABEL: define void @conflicting_cast(
; CHECK-SAME: i1 [[CMP_I8:%.*]]) {
; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [2 x i32], align 4
; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 2
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMP_I8]], i32 1, i32 2
; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP1]], align 2
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i16, ptr [[ACCUM_I_FLAT]], i32 0
; CHECK-NEXT: store i16 [[TMP3]], ptr [[GEP1]], align 2
; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i16, ptr [[ACCUM_I_FLAT]], i32 1
; CHECK-NEXT: store i16 [[TMP3]], ptr [[GEP2]], align 2
; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 1
; CHECK-NEXT: store i32 [[TMP4]], ptr [[GEP3]], align 4
; CHECK-NEXT: ret void
;
%accum.i.flat = alloca [2 x i32], align 4
%i = alloca i8, align 4
%select.i8 = select i1 %cmp.i8, i8 1, i8 2
store i8 %select.i8, ptr %i
%i8.load = load i8, ptr %i
%z = zext i8 %i8.load to i16
%gep1 = getelementptr i16, ptr %accum.i.flat, i32 0
store i16 %z, ptr %gep1, align 2
%gep2 = getelementptr i16, ptr %accum.i.flat, i32 1
store i16 %z, ptr %gep2, align 2
%z2 = zext i8 %i8.load to i32
%gep3 = getelementptr i32, ptr %accum.i.flat, i32 1
store i32 %z2, ptr %gep3, align 4
ret void
}
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