derek.holloway
7502bf64a4
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108 lines
3.3 KiB
LLVM
108 lines
3.3 KiB
LLVM
; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
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; If the "rx = #N, vsetq(rx)" get reordered with the rest, update the test.
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; v32i16 -> v32i8
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; CHECK-LABEL: f0:
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; CHECK: r[[R0:[0-9]+]] = #32
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; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK: v[[V1:[0-9]+]].b = vpacke({{.*}},v[[V0]].h)
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; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
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; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
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define void @f0(ptr %a0, ptr %a1) #0 {
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%v0 = load <32 x i16>, ptr %a0, align 128
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%v1 = trunc <32 x i16> %v0 to <32 x i8>
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store <32 x i8> %v1, ptr %a1, align 128
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ret void
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}
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; v32i32 -> v32i8
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; CHECK-LABEL: f1:
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; CHECK: r[[R0:[0-9]+]] = #32
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; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK: v[[V1:[0-9]+]].b = vdeale({{.*}},v[[V0]].b)
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; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
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; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
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define void @f1(ptr %a0, ptr %a1) #0 {
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%v0 = load <32 x i32>, ptr %a0, align 128
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%v1 = trunc <32 x i32> %v0 to <32 x i8>
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store <32 x i8> %v1, ptr %a1, align 128
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ret void
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}
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; v64i16 -> v64i8
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; CHECK-LABEL: f2:
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; CHECK: r[[R0:[0-9]+]] = #64
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; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK: v[[V1:[0-9]+]].b = vpacke({{.*}},v[[V0]].h)
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; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
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; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
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define void @f2(ptr %a0, ptr %a1) #0 {
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%v0 = load <64 x i16>, ptr %a0, align 128
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%v1 = trunc <64 x i16> %v0 to <64 x i8>
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store <64 x i8> %v1, ptr %a1, align 128
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ret void
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}
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; v64i32 -> v64i8
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; CHECK-LABEL: f3:
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; CHECK-DAG: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK-DAG: v[[V1:[0-9]+]] = vmem(r0+#1)
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; CHECK-DAG: q[[Q0:[0-3]]] = vsetq
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; CHECK: v[[V2:[0-9]+]].h = vpacke(v[[V1]].w,v[[V0]].w)
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; CHECK: v[[V3:[0-9]+]].b = vpacke({{.*}},v[[V2]].h)
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; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V3]]
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define void @f3(ptr %a0, ptr %a1) #0 {
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%v0 = load <64 x i32>, ptr %a0, align 128
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%v1 = trunc <64 x i32> %v0 to <64 x i8>
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store <64 x i8> %v1, ptr %a1, align 128
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ret void
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}
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; v16i32 -> v16i16
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; CHECK-LABEL: f4:
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; CHECK: r[[R0:[0-9]+]] = #32
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; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK: v[[V1:[0-9]+]].h = vpacke({{.*}},v[[V0]].w)
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; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
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; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
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define void @f4(ptr %a0, ptr %a1) #0 {
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%v0 = load <16 x i32>, ptr %a0, align 128
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%v1 = trunc <16 x i32> %v0 to <16 x i16>
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store <16 x i16> %v1, ptr %a1, align 128
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ret void
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}
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; v32i32 -> v32i16
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; CHECK-LABEL: f5:
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; CHECK: r[[R0:[0-9]+]] = #64
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; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK: v[[V1:[0-9]+]].h = vpacke({{.*}},v[[V0]].w)
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; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])
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; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]
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define void @f5(ptr %a0, ptr %a1) #0 {
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%v0 = load <32 x i32>, ptr %a0, align 128
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%v1 = trunc <32 x i32> %v0 to <32 x i16>
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store <32 x i16> %v1, ptr %a1, align 128
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ret void
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}
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; v8i32 -> v8i8
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; CHECK-LABEL: f6:
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; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)
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; CHECK: v[[V1:[0-9]+]].b = vdeale({{.*}},v[[V0]].b)
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; CHECK: vmem(r[[R0:[0-9]+]]+#0) = v[[V1]]
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; CHECK-DAG: r[[R1:[0-9]+]] = memw(r[[R0]]+#0)
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; CHECK-DAG: r[[R2:[0-9]+]] = memw(r[[R0]]+#4)
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; CHECK: memd(r1+#0) = r[[R2]]:[[R1]]
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define void @f6(ptr %a0, ptr %a1) #0 {
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%v0 = load <8 x i32>, ptr %a0, align 128
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%v1 = trunc <8 x i32> %v0 to <8 x i8>
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store <8 x i8> %v1, ptr %a1, align 128
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ret void
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}
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attributes #0 = { "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b,-packets" }
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