derek.holloway
7502bf64a4
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32 lines
1007 B
LLVM
32 lines
1007 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; Check that we generate zero-extends, instead of just shifting and oring
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; registers (which can contain sign-extended negative values).
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define i32 @fred(i8 %a0, i8 %a1, i8 %a2, i8 %a3) #0 {
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; CHECK-LABEL: fred:
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; CHECK: // %bb.0: // %b4
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = and(r1,#255)
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; CHECK-NEXT: r3 = and(r3,#255)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = insert(r1,#24,#8)
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; CHECK-NEXT: r2 = insert(r3,#24,#8)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = combine(r2.l,r0.l)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b4:
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%v5 = insertelement <4 x i8> undef, i8 %a0, i32 0
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%v6 = insertelement <4 x i8> %v5, i8 %a1, i32 1
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%v7 = insertelement <4 x i8> %v6, i8 %a2, i32 2
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%v8 = insertelement <4 x i8> %v7, i8 %a3, i32 3
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%v9 = bitcast <4 x i8> %v8 to i32
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ret i32 %v9
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}
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attributes #0 = { nounwind readnone }
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