derek.holloway
7502bf64a4
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45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s
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; REQUIRES: asserts
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; Test that the DAG combiner doesn't assert because it attempts to replace
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; the chain of a post-increment store based upon alias information. The code
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; in DAGCombiner is unable to convert indexed stores.
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; Function Attrs: nounwind
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define void @f0(i32 %a0, ptr %a1, ptr %a2) #0 {
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b0:
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switch i32 %a0, label %b5 [
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i32 67830273, label %b1
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i32 67502595, label %b3
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]
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b1: ; preds = %b0
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br i1 undef, label %b2, label %b5
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b2: ; preds = %b1
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br label %b5
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b3: ; preds = %b0
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br i1 undef, label %b4, label %b5
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b4: ; preds = %b3
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store i32 0, ptr %a2, align 1, !tbaa !0
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%v1 = getelementptr inbounds i8, ptr %a1, i32 4
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%v3 = load i32, ptr %v1, align 4, !tbaa !5
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%v4 = getelementptr inbounds i8, ptr %a2, i32 4
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store i32 %v3, ptr %v4, align 1, !tbaa !5
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br label %b5
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b5: ; preds = %b4, %b3, %b2, %b1, %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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!0 = !{!1, !2, i64 0}
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!1 = !{!"", !2, i64 0, !2, i64 4}
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!2 = !{!"long", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!1, !2, i64 4}
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