derek.holloway
7502bf64a4
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144 lines
3.6 KiB
LLVM
144 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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target triple = "hexagon"
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define i32 @add_v32i32(<32 x i32> %vec) #0 {
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; CHECK-LABEL: add_v32i32:
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; CHECK: {
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; CHECK: [[R0:v[0-9]+]] = valign([[_:v[0-9]+]],v0,{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R1:v[0-9]+]].w = vadd(v0.w,[[R0]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R2:v[0-9]+]] = valign([[_:v[0-9]+]],[[R1]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R3:v[0-9]+]].w = vadd([[R1]].w,[[R2]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R4:v[0-9]+]] = valign([[_:v[0-9]+]],[[R3]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R5:v[0-9]+]].w = vadd([[R3]].w,[[R4]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R6:v[0-9]+]] = valign([[_:v[0-9]+]],[[R5]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R7:v[0-9]+]].w = vadd([[R5]].w,[[R6]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R8:v[0-9]+]] = valign([[_:v[0-9]+]],[[R7]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R9:v[0-9]+]].w = vadd([[R7]].w,[[R8]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: r0 = vextract([[R9]],{{.+}})
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; CHECK: }
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entry:
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%r = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %vec)
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ret i32 %r
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}
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define i32 @add_v16i32(<16 x i32> %vec) #0 {
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; CHECK-LABEL: add_v16i32:
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; CHECK: {
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; CHECK: [[R0:v[0-9]+]] = valign([[_:v[0-9]+]],v0,{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R1:v[0-9]+]].w = vadd(v0.w,[[R0]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R2:v[0-9]+]] = valign([[_:v[0-9]+]],[[R1]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R3:v[0-9]+]].w = vadd([[R1]].w,[[R2]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R4:v[0-9]+]] = valign([[_:v[0-9]+]],[[R3]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R5:v[0-9]+]].w = vadd([[R3]].w,[[R4]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: [[R6:v[0-9]+]] = valign([[_:v[0-9]+]],[[R5]],{{.+}})
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; CHECK: }
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; CHECK: {
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; CHECK: [[R7:v[0-9]+]].w = vadd([[R5]].w,[[R6]].w)
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; CHECK: }
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; CHECK: {
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; CHECK: r0 = vextract([[R7]],{{.+}})
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; CHECK: }
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entry:
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%r = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %vec)
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ret i32 %r
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}
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define i32 @add_v8i32(<8 x i32> %vec) #0 {
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; CHECK-LABEL: add_v8i32:
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; CHECK: {
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; CHECK: r[[RS1:[0-9]+:[0-9]+]] = vaddw(r1:0,r5:4)
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; CHECK: r[[R6:[0-9]+:[0-9]+]] = memd(r29+#0)
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; CHECK: }
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; CHECK: {
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; CHECK: r[[RS2:[0-9]+:[0-9]+]] = vaddw(r3:2,r[[R6]])
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; CHECK: }
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; CHECK: {
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; CHECK: r[[RS3:[0-9]+:[0-9]+]] = vaddw(r[[RS1]],r[[RS2]])
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; CHECK: }
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; CHECK: {
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;; TODO: combine and double register add can be optimized to single register add.
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; CHECK: r[[RS4:[0-9]+:[0-9]+]] = combine(#0,r{{[0-9]+}})
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; CHECK: }
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; CHECK: {
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; CHECK: r1:0 = vaddw(r[[RS3]],r[[RS4]])
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entry:
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%r = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %vec)
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ret i32 %r
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}
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define i32 @add_v64i32(<64 x i32> %vec) #0 {
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; CHECK-LABEL: add_v64i32:
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; CHECK: vadd
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; CHECK: valign
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; CHECK: vadd
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; CHECK: valign
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; CHECK: vadd
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; CHECK: valign
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; CHECK: vadd
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; CHECK: valign
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; CHECK: vadd
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; CHECK: valign
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; CHECK: vadd
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entry:
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%r = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %vec)
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ret i32 %r
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}
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;; Non-pow2 vectors are scalarized.
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define i32 @add_v12i32(<12 x i32> %vec) #0 {
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; CHECK-LABEL: add_v12i32:
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; CHECK: [[RS0:r[0-9]+]] = add(r0,r1)
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; CHECK: [[RS1:r[0-9]+]] += add([[RS0]],r{{[0-9]+}})
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; CHECK: [[RS2:r[0-9]+]] += add([[RS1]],r{{[0-9]+}})
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; CHECK: [[RS3:r[0-9]+]] += add([[RS2]],r{{[0-9]+}})
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; CHECK: [[RS4:r[0-9]+]] += add([[RS3]],r{{[0-9]+}})
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; CHECK: [[RS5:r[0-9]+]] += add([[RS4]],r{{[0-9]+}})
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entry:
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%r = call i32 @llvm.vector.reduce.add.v12i32(<12 x i32> %vec)
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ret i32 %r
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}
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define i32 @add_v3i32(<3 x i32> %vec) #0 {
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; CHECK-LABEL: add_v3i32:
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; CHECK: r{{[0-9]+}} += add(r{{[0-9]+}},r{{[0-9]+}})
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entry:
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%r = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %vec)
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ret i32 %r
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv68" "target-features"="+hvx,+hvx-length128b" }
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