derek.holloway
7502bf64a4
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190 lines
4.6 KiB
LLVM
190 lines
4.6 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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;
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; Test that all FP ordered compare instructions generate the correct
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; post-processing to accommodate NaNs.
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;
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; Specifically for ordered FP compares, we have to check if one of
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; the operands was a NaN to comform to the semantics of the ordered
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; fcmp bitcode instruction
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;
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target triple = "hexagon"
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;
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; Functions for float:
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;
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
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; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_oeq_f(float %val, float %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp oeq float %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
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; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
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; CHECK: [[REG2:p([0-3])]] = or([[REG0]],[[REG1]])
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; CHECK: r0 = mux([[REG2]],#0,#1)
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;
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define i32 @compare_one_f(float %val, float %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp one float %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r0,r1)
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; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_ogt_f(float %val, float %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp ogt float %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r1,r0)
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; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r1,r0)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_ole_f(float %val, float %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp ole float %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r0,r1)
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; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_oge_f(float %val, float %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp oge float %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r1,r0)
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; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r1,r0)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_olt_f(float %val, float %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp olt float %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; Functions for double:
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;
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = dfcmp.eq(r1:0,r3:2)
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; CHECK-DAG: [[REG1:p([0-3])]] = dfcmp.uo(r1:0,r3:2)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_oeq_d(double %val, double %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp oeq double %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = dfcmp.eq(r1:0,r3:2)
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; CHECK-DAG: [[REG1:p([0-3])]] = dfcmp.uo(r1:0,r3:2)
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; CHECK: [[REG2:p([0-3])]] = or([[REG0]],[[REG1]])
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; CHECK: r0 = mux([[REG2]],#0,#1)
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;
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define i32 @compare_one_d(double %val, double %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp one double %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = dfcmp.gt(r1:0,r3:2)
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; CHECK-DAG: [[REG1:p([0-3])]] = dfcmp.uo(r1:0,r3:2)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_ogt_d(double %val, double %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp ogt double %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = dfcmp.ge(r3:2,r1:0)
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; CHECK-DAG: [[REG1:p([0-3])]] = dfcmp.uo(r3:2,r1:0)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_ole_d(double %val, double %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp ole double %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = dfcmp.ge(r1:0,r3:2)
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; CHECK-DAG: [[REG1:p([0-3])]] = dfcmp.uo(r1:0,r3:2)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_oge_d(double %val, double %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp oge double %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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;
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; CHECK-DAG: [[REG0:p([0-3])]] = dfcmp.gt(r3:2,r1:0)
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; CHECK-DAG: [[REG1:p([0-3])]] = dfcmp.uo(r3:2,r1:0)
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; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
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; CHECK: r0 = mux([[REG2]],#1,#0)
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;
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define i32 @compare_olt_d(double %val, double %val2) local_unnamed_addr #0 {
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entry:
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%cmpinf = fcmp olt double %val, %val2
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%0 = zext i1 %cmpinf to i32
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ret i32 %0
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}
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