derek.holloway
7502bf64a4
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90 lines
5.1 KiB
LLVM
90 lines
5.1 KiB
LLVM
; RUN: llc -mtriple=hexagon -mattr=+hvxv75,+hvx-length128b < %s | FileCheck %s
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; Test v32i1 store operation
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; CHECK-LABEL: test_v32i1_store:
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; CHECK: memw(r{{[0-9]+}}+#0) = r{{[0-9]+}}
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define void @test_v32i1_store(i32 %idx) {
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entry:
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%ptr = tail call ptr @malloc(i64 1088)
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%aligned_ptr_int = ptrtoint ptr %ptr to i32
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%aligned_int = add i32 %aligned_ptr_int, 63
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%aligned_int_masked = and i32 %aligned_int, -64
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%aligned_ptr = inttoptr i32 %aligned_int_masked to ptr
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%shifted = shl i32 %idx, 3
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%cond = icmp slt i32 %shifted, 100
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%pred_elem = insertelement <32 x i1> poison, i1 %cond, i64 0
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%pred_broadcast = shufflevector <32 x i1> %pred_elem, <32 x i1> poison, <32 x i32> zeroinitializer
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%mask = and <32 x i1> %pred_broadcast, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
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store <32 x i1> %mask, ptr %aligned_ptr, align 64
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ret void
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}
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; Test v32i1 load operation
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; CHECK-LABEL: test_v32i1_load:
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; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+#0)
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define <32 x i1> @test_v32i1_load(ptr %ptr) {
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entry:
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%pred = load <32 x i1>, ptr %ptr, align 64
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ret <32 x i1> %pred
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}
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; Test v64i1 store operation
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; CHECK-LABEL: test_v64i1_store:
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; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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define void @test_v64i1_store(i32 %idx) {
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entry:
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%ptr = tail call ptr @malloc(i64 1088)
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%aligned_ptr_int = ptrtoint ptr %ptr to i32
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%aligned_int = add i32 %aligned_ptr_int, 63
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%aligned_int_masked = and i32 %aligned_int, -64
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%aligned_ptr = inttoptr i32 %aligned_int_masked to ptr
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%shifted = shl i32 %idx, 3
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%cond = icmp slt i32 %shifted, 100
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%pred_elem = insertelement <64 x i1> poison, i1 %cond, i64 0
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%pred_broadcast = shufflevector <64 x i1> %pred_elem, <64 x i1> poison, <64 x i32> zeroinitializer
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%mask = and <64 x i1> %pred_broadcast, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
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store <64 x i1> %mask, ptr %aligned_ptr, align 64
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ret void
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}
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; Test v64i1 load operation
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; CHECK-LABEL: test_v64i1_load:
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; CHECK: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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define <64 x i1> @test_v64i1_load(ptr %ptr) {
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entry:
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%pred = load <64 x i1>, ptr %ptr, align 64
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ret <64 x i1> %pred
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}
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; Test v128i1 store operation
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; CHECK-LABEL: test_v128i1_store:
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; CHECK: memd(r{{[0-9]+}}+#0) = r{{[0-9]+}}:{{[0-9]+}}
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; CHECK: memd(r{{[0-9]+}}+#{{[0-9]+}}) = r{{[0-9]+}}:{{[0-9]+}}
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define void @test_v128i1_store(i32 %idx) {
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entry:
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%ptr = tail call ptr @malloc(i64 1088)
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%aligned_ptr_int = ptrtoint ptr %ptr to i32
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%aligned_int = add i32 %aligned_ptr_int, 63
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%aligned_int_masked = and i32 %aligned_int, -64
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%aligned_ptr = inttoptr i32 %aligned_int_masked to ptr
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%shifted = shl i32 %idx, 3
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%cond = icmp slt i32 %shifted, 100
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%pred_elem = insertelement <128 x i1> poison, i1 %cond, i64 0
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%pred_broadcast = shufflevector <128 x i1> %pred_elem, <128 x i1> poison, <128 x i32> zeroinitializer
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%mask = and <128 x i1> %pred_broadcast, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
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store <128 x i1> %mask, ptr %aligned_ptr, align 64
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ret void
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}
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; Test v128i1 load operation
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; CHECK-LABEL: test_v128i1_load:
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; CHECK-DAG: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#0)
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; CHECK-DAG: r{{[0-9]+}}:{{[0-9]+}} = memd(r{{[0-9]+}}+#{{[0-9]+}})
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define <128 x i1> @test_v128i1_load(ptr %ptr) {
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entry:
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%pred = load <128 x i1>, ptr %ptr, align 64
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ret <128 x i1> %pred
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}
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declare ptr @malloc(i64)
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