derek.holloway
7502bf64a4
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61 lines
1.9 KiB
LLVM
61 lines
1.9 KiB
LLVM
;; RUN: llc --mtriple=hexagon --mcpu=hexagonv81 --mattr=+hvxv81,+hvx-length128b %s -o - | FileCheck %s
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define void @mul_and_sub_1(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {
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entry:
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%AVec = load <32 x float>, ptr %A, align 4
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%BVec = load <32 x float>, ptr %B, align 4
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%CVec = load <32 x float>, ptr %C, align 4
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%AtBVec = fmul <32 x float> %AVec, %BVec
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%DVec = fsub <32 x float> %CVec, %AtBVec
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store <32 x float> %DVec, ptr %D, align 4
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ret void
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}
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;; CHECK: mul_and_sub_1
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;; CHECK: vsub(v{{[0-9]+}}.sf,v{{[0-9]+}}.qf32)
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define void @mul_and_sub_2(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {
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entry:
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%AVec = load <32 x float>, ptr %A, align 4
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%BVec = load <32 x float>, ptr %B, align 4
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%CVec = load <32 x float>, ptr %C, align 4
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%AtBVec = fmul <32 x float> %AVec, %BVec
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%DVec = fsub <32 x float> %AtBVec, %CVec
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store <32 x float> %DVec, ptr %D, align 4
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ret void
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}
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;; CHECK: mul_and_sub_2
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;; CHECK: vsub(v{{[0-9]+}}.qf32,v{{[0-9]+}}.sf)
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define void @mul_and_sub_3(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {
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entry:
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%AVec = load <64 x half>, ptr %A, align 4
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%BVec = load <64 x half>, ptr %B, align 4
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%CVec = load <64 x half>, ptr %C, align 4
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%AtBVec = fmul <64 x half> %AVec, %BVec
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%DVec = fsub <64 x half> %CVec, %AtBVec
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store <64 x half> %DVec, ptr %D, align 4
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ret void
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}
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;; CHECK: mul_and_sub_3
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;; CHECK: vsub(v{{[0-9]+}}.hf,v{{[0-9]+}}.qf16)
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define void @mul_and_sub_4(ptr readonly %A, ptr readonly %B, ptr readonly %C, ptr writeonly %D) {
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entry:
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%AVec = load <64 x half>, ptr %A, align 4
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%BVec = load <64 x half>, ptr %B, align 4
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%CVec = load <64 x half>, ptr %C, align 4
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%AtBVec = fmul <64 x half> %AVec, %BVec
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%DVec = fsub <64 x half> %AtBVec, %CVec
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store <64 x half> %DVec, ptr %D, align 4
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ret void
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}
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;; CHECK: mul_and_sub_4
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;; CHECK: vsub(v{{[0-9]+}}.qf16,v{{[0-9]+}}.hf)
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