derek.holloway
7502bf64a4
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75 lines
2.0 KiB
LLVM
75 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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;
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; CHECK-LABEL: foo_128_2x
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; Check that bitcast is computed corrected by fixing up a predicate register
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; before compressing it.
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; CHECK: v[[V1:[0-9]+]].b = vdeal(v{{[0-9]+}}.b)
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; Check that the resulting register pair has the registers in the right order.
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; CHECK: vdeal
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; CHECK: vdeal
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; CHECK: v[[V1:[0-9]+]]:[[V0:[0-9]+]] = vshuff
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: vmem(r[[RA:[0-9]+]]+#0) = v[[V0]]
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = memw(r1+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = memw(r1+#4)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r31:30 = dealloc_return(r30):raw
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; CHECK-NEXT: }
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define i64 @foo_128_2x(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%v0 = icmp ugt <64 x i16> %a0, %a1
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%v1 = bitcast <64 x i1> %v0 to i64
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ret i64 %v1
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}
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;; The remaining test cases only check the bitvector compression stage, which is
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;; the only distinction.
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; CHECK-LABEL: foo_128_4x
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; CHECK: v[[V1:[0-9]+]].h = vdeal(v{{[0-9]+}}.h)
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; CHECK: v{{[0-9]+}}.b = vdeal(v[[V1]].b)
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; CHECK: vdeal
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; CHECK: vdeal
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; CHECK: vshuff
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define i32 @foo_128_4x(<32 x i16> %a0, <32 x i16> %a1) #0 {
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%v0 = icmp ugt <32 x i16> %a0, %a1
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%v1 = bitcast <32 x i1> %v0 to i32
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ret i32 %v1
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}
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; CHECK-LABEL: foo_64_2x
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; CHECK: v{{[0-9]+}}.b = vdeal(v{{[0-9]+}}.b)
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; CHECK: vdeal
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; CHECK: vdeal
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; CHECK: vshuff
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define i32 @foo_64_2x(<32 x i16> %a0, <32 x i16> %a1) #1 {
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%v0 = icmp ugt <32 x i16> %a0, %a1
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%v1 = bitcast <32 x i1> %v0 to i32
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ret i32 %v1
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}
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; CHECK-LABEL: foo_64_4x
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; CHECK: v[[V1:[0-9]+]].h = vdeal(v{{[0-9]+}}.h)
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; CHECK: v{{[0-9]+}}.b = vdeal(v[[V1]].b)
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; CHECK: vdeal
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; CHECK: vdeal
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; CHECK: vshuff
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define i16 @foo_64_4x(<16 x i16> %a0, <16 x i16> %a1) #1 {
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%v0 = icmp ugt <16 x i16> %a0, %a1
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%v1 = bitcast <16 x i1> %v0 to i16
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ret i16 %v1
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv68" "target-features"="+hvx,+hvx-length128b,-packets" }
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attributes #1 = { nounwind readnone "target-cpu"="hexagonv68" "target-features"="+hvx,+hvx-length64b,-packets" }
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