derek.holloway
7502bf64a4
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30 lines
919 B
LLVM
30 lines
919 B
LLVM
; RUN: llc -mtriple=hexagon < %s
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; REQUIRES: asserts
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; Test that the pipeliner doesn't assert in orderDependence because
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; the check for OrderAfterDef precedeence is in the wrong spot.
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%s.0 = type <{ i8, [20 x %s.1] }>
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%s.1 = type { i16, i16 }
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; Function Attrs: nounwind optsize ssp
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define void @f0() #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ %v3, %b1 ], [ 0, %b0 ]
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%v1 = getelementptr inbounds %s.0, ptr undef, i32 0, i32 1, i32 %v0, i32 0
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store i16 0, ptr %v1, align 1
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%v2 = getelementptr inbounds %s.0, ptr undef, i32 0, i32 1, i32 %v0, i32 1
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store i16 -1, ptr %v2, align 1
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%v3 = add nsw i32 %v0, 1
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%v4 = icmp eq i32 %v3, 20
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br i1 %v4, label %b2, label %b1
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b2: ; preds = %b1, %b0
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ret void
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}
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attributes #0 = { nounwind optsize ssp "target-cpu"="hexagonv55" }
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