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43 lines
1.3 KiB
LLVM
43 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s
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; CHECK: vmem
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; CHECK: vmem
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; CHECK-NOT: r{{[0-9]*}} = add(r30,#-256)
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; CHECK: vmem
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; CHECK: vmem
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(ptr %a0, ptr %a1, i32 %a2, ptr %a3, i32 %a4) #0 {
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b0:
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%v0 = alloca ptr, align 4
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%v1 = alloca ptr, align 4
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%v2 = alloca i32, align 4
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%v3 = alloca ptr, align 4
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%v4 = alloca i32, align 4
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%v5 = alloca <16 x i32>, align 64
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%v6 = alloca <32 x i32>, align 128
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store ptr %a0, ptr %v0, align 4
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store ptr %a1, ptr %v1, align 4
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store i32 %a2, ptr %v2, align 4
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store ptr %a3, ptr %v3, align 4
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store i32 %a4, ptr %v4, align 4
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%v7 = load ptr, ptr %v0, align 4
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%v9 = load <16 x i32>, ptr %v7, align 64
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%v10 = load ptr, ptr %v0, align 4
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%v11 = getelementptr inbounds i8, ptr %v10, i32 64
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%v13 = load <16 x i32>, ptr %v11, align 64
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%v14 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v9, <16 x i32> %v13)
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store <32 x i32> %v14, ptr %v6, align 128
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%v15 = load ptr, ptr %v3, align 4
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%v17 = load <16 x i32>, ptr %v15, align 64
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store <16 x i32> %v17, ptr %v5, align 64
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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