derek.holloway
7502bf64a4
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37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b \
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; RUN: -enable-hexagon-vector-print < %s | FileCheck %s
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; Test coverage for HexagonVectorPrint: exercise the W (double vector)
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; and V (single vector) register printing paths.
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; Use two stores so that the V result is not entirely consumed by a .new
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; store, leaving a live V register for the vector-print pass to instrument.
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; CHECK-LABEL: test_vecprint_v:
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; CHECK: InlineAsm Start
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; CHECK: .word
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; CHECK: InlineAsm End
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define void @test_vecprint_v(<32 x i32> %a, <32 x i32> %b, ptr %p, ptr %q) #0 {
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entry:
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%add = add <32 x i32> %a, %b
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store <32 x i32> %add, ptr %p, align 128
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store <32 x i32> %add, ptr %q, align 128
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ret void
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}
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; The W register case should emit inline asm blocks for each V sub-register.
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; CHECK-LABEL: test_vecprint_w:
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; CHECK: InlineAsm Start
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; CHECK: .word
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; CHECK: InlineAsm End
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; CHECK: InlineAsm Start
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; CHECK: .word
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; CHECK: InlineAsm End
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define void @test_vecprint_w(<64 x i32> %a, <64 x i32> %b, ptr %p) #0 {
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entry:
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%add = add <64 x i32> %a, %b
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store <64 x i32> %add, ptr %p, align 128
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ret void
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}
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attributes #0 = { nounwind }
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