derek.holloway
7502bf64a4
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80 lines
2.2 KiB
YAML
80 lines
2.2 KiB
YAML
# RUN: llc -march=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b \
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# RUN: -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s
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# Test that the operands are swapped for Add if the second operand
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# is a qf32 to sf conversion. V6_vadd_qf32_mix supports first operand
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# as qf32.
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# CHECK-LABEL: name: qfpAddMix
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# CHECK: %[[REG:([0-9]+)]]:hvxvr = V6_vmpy_qf32_sf
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# CHECK: V6_vadd_qf32_mix %[[REG]]
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---
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name: qfpAddMix
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0, $r1, $r2, $r3
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%0:intregs = COPY $r0
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%1:intregs = COPY $r1
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%2:intregs = COPY $r2
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%3:hvxvr = V6_vL32Ub_ai %0:intregs, 0
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%4:hvxvr = V6_vL32Ub_ai %1:intregs, 0
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%5:hvxvr = V6_vL32Ub_ai %2:intregs, 0
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%6:hvxvr = V6_vmpy_qf32_sf %4, %5
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%7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr
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%8:hvxvr = V6_vadd_sf %3:hvxvr, %7:hvxvr
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...
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# Test that we do not generate V6_vsub_qf32_mix for the below test.
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# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf32
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# is passed as second operand. As sub is not commutative, we should not
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# generate the mix instruction.
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# CHECK-LABEL: name: qfpSubNoMix
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# CHECK-NOT: V6_vsub_qf32_mix
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---
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name: qfpSubNoMix
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0, $r1, $r2, $r3
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%0:intregs = COPY $r0
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%1:intregs = COPY $r1
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%2:intregs = COPY $r2
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%3:hvxvr = V6_vL32Ub_ai %0:intregs, 0
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%4:hvxvr = V6_vL32Ub_ai %1:intregs, 0
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%5:hvxvr = V6_vL32Ub_ai %2:intregs, 0
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%6:hvxvr = V6_vmpy_qf32_sf %4, %5
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%7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr
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%8:hvxvr = V6_vsub_sf %3:hvxvr, %7:hvxvr
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...
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# Test that we do generate V6_vsub_qf32_mix for the below test.
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# V6_vsub_qf32_mix only allowes qf32 as first operand. In the test qf32
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# is passed as first operand. So, V6_vsub_qf32_mix must be generated.
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# CHECK-LABEL: name: qfpSubMix
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# CHECK: V6_vsub_qf32_mix
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---
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name: qfpSubMix
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0, $r1, $r2, $r3
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%0:intregs = COPY $r0
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%1:intregs = COPY $r1
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%2:intregs = COPY $r2
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%3:hvxvr = V6_vL32Ub_ai %0:intregs, 0
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%4:hvxvr = V6_vL32Ub_ai %1:intregs, 0
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%5:hvxvr = V6_vL32Ub_ai %2:intregs, 0
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%6:hvxvr = V6_vmpy_qf32_sf %4, %5
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%7:hvxvr = V6_vconv_sf_qf32 %6:hvxvr
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%8:hvxvr = V6_vsub_sf %7:hvxvr, %3:hvxvr
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...
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