derek.holloway
7502bf64a4
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71 lines
2.2 KiB
LLVM
71 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
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define void @register_xr1() nounwind {
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; CHECK-LABEL: register_xr1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: xvldi $xr1, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr1}"()
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ret void
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}
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define void @register_xr7() nounwind {
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; CHECK-LABEL: register_xr7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: xvldi $xr7, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr7}"()
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ret void
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}
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define void @register_xr23() nounwind {
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; CHECK-LABEL: register_xr23:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: xvldi $xr23, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: ret
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entry:
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%0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr23}"()
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ret void
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}
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;; The lower 64-bit of the vector register '$xr31' is overlapped with
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;; the floating-point register '$f31' ('$fs7'). And '$f31' ('$fs7')
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;; is a callee-saved register which is preserved across calls.
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;; That's why the fst.d and fld.d instructions are emitted.
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define void @register_xr31() nounwind {
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; LA32-LABEL: register_xr31:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: addi.w $sp, $sp, -16
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; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
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; LA32-NEXT: #APP
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; LA32-NEXT: xvldi $xr31, 1
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; LA32-NEXT: #NO_APP
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; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
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; LA32-NEXT: addi.w $sp, $sp, 16
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; LA32-NEXT: ret
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;
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; LA64-LABEL: register_xr31:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: addi.d $sp, $sp, -16
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; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
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; LA64-NEXT: #APP
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; LA64-NEXT: xvldi $xr31, 1
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; LA64-NEXT: #NO_APP
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; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
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; LA64-NEXT: addi.d $sp, $sp, 16
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; LA64-NEXT: ret
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entry:
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%0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr31}"()
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ret void
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}
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