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TheRock/compiler/amd-llvm/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll
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2026-09-02 16:34:47 -07:00

52 lines
1.7 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvreplve.b(<32 x i8>, i32)
define <32 x i8> @lasx_xvreplve_b(<32 x i8> %va, i32 %b) nounwind {
; CHECK-LABEL: lasx_xvreplve_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvreplve.b $xr0, $xr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <32 x i8> @llvm.loongarch.lasx.xvreplve.b(<32 x i8> %va, i32 %b)
ret <32 x i8> %res
}
declare <16 x i16> @llvm.loongarch.lasx.xvreplve.h(<16 x i16>, i32)
define <16 x i16> @lasx_xvreplve_h(<16 x i16> %va, i32 %b) nounwind {
; CHECK-LABEL: lasx_xvreplve_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvreplve.h $xr0, $xr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <16 x i16> @llvm.loongarch.lasx.xvreplve.h(<16 x i16> %va, i32 %b)
ret <16 x i16> %res
}
declare <8 x i32> @llvm.loongarch.lasx.xvreplve.w(<8 x i32>, i32)
define <8 x i32> @lasx_xvreplve_w(<8 x i32> %va, i32 %b) nounwind {
; CHECK-LABEL: lasx_xvreplve_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvreplve.w $xr0, $xr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <8 x i32> @llvm.loongarch.lasx.xvreplve.w(<8 x i32> %va, i32 %b)
ret <8 x i32> %res
}
declare <4 x i64> @llvm.loongarch.lasx.xvreplve.d(<4 x i64>, i32)
define <4 x i64> @lasx_xvreplve_d(<4 x i64> %va, i32 %b) nounwind {
; CHECK-LABEL: lasx_xvreplve_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvreplve.d $xr0, $xr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvreplve.d(<4 x i64> %va, i32 %b)
ret <4 x i64> %res
}