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TheRock/compiler/amd-llvm/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslt.b(<32 x i8>, <32 x i8>)
define <32 x i8> @lasx_xvslt_b(<32 x i8> %va, <32 x i8> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.b $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <32 x i8> @llvm.loongarch.lasx.xvslt.b(<32 x i8> %va, <32 x i8> %vb)
ret <32 x i8> %res
}
declare <16 x i16> @llvm.loongarch.lasx.xvslt.h(<16 x i16>, <16 x i16>)
define <16 x i16> @lasx_xvslt_h(<16 x i16> %va, <16 x i16> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.h $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <16 x i16> @llvm.loongarch.lasx.xvslt.h(<16 x i16> %va, <16 x i16> %vb)
ret <16 x i16> %res
}
declare <8 x i32> @llvm.loongarch.lasx.xvslt.w(<8 x i32>, <8 x i32>)
define <8 x i32> @lasx_xvslt_w(<8 x i32> %va, <8 x i32> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.w $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <8 x i32> @llvm.loongarch.lasx.xvslt.w(<8 x i32> %va, <8 x i32> %vb)
ret <8 x i32> %res
}
declare <4 x i64> @llvm.loongarch.lasx.xvslt.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvslt_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.d $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvslt.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
}
declare <32 x i8> @llvm.loongarch.lasx.xvslti.b(<32 x i8>, i32)
define <32 x i8> @lasx_xvslti_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.b $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <32 x i8> @llvm.loongarch.lasx.xvslti.b(<32 x i8> %va, i32 1)
ret <32 x i8> %res
}
declare <16 x i16> @llvm.loongarch.lasx.xvslti.h(<16 x i16>, i32)
define <16 x i16> @lasx_xvslti_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.h $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <16 x i16> @llvm.loongarch.lasx.xvslti.h(<16 x i16> %va, i32 1)
ret <16 x i16> %res
}
declare <8 x i32> @llvm.loongarch.lasx.xvslti.w(<8 x i32>, i32)
define <8 x i32> @lasx_xvslti_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.w $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <8 x i32> @llvm.loongarch.lasx.xvslti.w(<8 x i32> %va, i32 1)
ret <8 x i32> %res
}
declare <4 x i64> @llvm.loongarch.lasx.xvslti.d(<4 x i64>, i32)
define <4 x i64> @lasx_xvslti_d(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.d $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvslti.d(<4 x i64> %va, i32 1)
ret <4 x i64> %res
}
declare <32 x i8> @llvm.loongarch.lasx.xvslt.bu(<32 x i8>, <32 x i8>)
define <32 x i8> @lasx_xvslt_bu(<32 x i8> %va, <32 x i8> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_bu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.bu $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <32 x i8> @llvm.loongarch.lasx.xvslt.bu(<32 x i8> %va, <32 x i8> %vb)
ret <32 x i8> %res
}
declare <16 x i16> @llvm.loongarch.lasx.xvslt.hu(<16 x i16>, <16 x i16>)
define <16 x i16> @lasx_xvslt_hu(<16 x i16> %va, <16 x i16> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_hu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.hu $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <16 x i16> @llvm.loongarch.lasx.xvslt.hu(<16 x i16> %va, <16 x i16> %vb)
ret <16 x i16> %res
}
declare <8 x i32> @llvm.loongarch.lasx.xvslt.wu(<8 x i32>, <8 x i32>)
define <8 x i32> @lasx_xvslt_wu(<8 x i32> %va, <8 x i32> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_wu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.wu $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <8 x i32> @llvm.loongarch.lasx.xvslt.wu(<8 x i32> %va, <8 x i32> %vb)
ret <8 x i32> %res
}
declare <4 x i64> @llvm.loongarch.lasx.xvslt.du(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvslt_du(<4 x i64> %va, <4 x i64> %vb) nounwind {
; CHECK-LABEL: lasx_xvslt_du:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslt.du $xr0, $xr0, $xr1
; CHECK-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvslt.du(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
}
declare <32 x i8> @llvm.loongarch.lasx.xvslti.bu(<32 x i8>, i32)
define <32 x i8> @lasx_xvslti_bu(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_bu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.bu $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <32 x i8> @llvm.loongarch.lasx.xvslti.bu(<32 x i8> %va, i32 1)
ret <32 x i8> %res
}
declare <16 x i16> @llvm.loongarch.lasx.xvslti.hu(<16 x i16>, i32)
define <16 x i16> @lasx_xvslti_hu(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_hu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.hu $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <16 x i16> @llvm.loongarch.lasx.xvslti.hu(<16 x i16> %va, i32 1)
ret <16 x i16> %res
}
declare <8 x i32> @llvm.loongarch.lasx.xvslti.wu(<8 x i32>, i32)
define <8 x i32> @lasx_xvslti_wu(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_wu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.wu $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <8 x i32> @llvm.loongarch.lasx.xvslti.wu(<8 x i32> %va, i32 1)
ret <8 x i32> %res
}
declare <4 x i64> @llvm.loongarch.lasx.xvslti.du(<4 x i64>, i32)
define <4 x i64> @lasx_xvslti_du(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvslti_du:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvslti.du $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvslti.du(<4 x i64> %va, i32 1)
ret <4 x i64> %res
}
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