TheRock/compiler/amd-llvm/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64

define <32 x i8> @insert_extract_v32i8(<32 x i8> %a) nounwind {
; CHECK-LABEL: insert_extract_v32i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvpermi.d $xr1, $xr0, 14
; CHECK-NEXT:    vpickve2gr.b $a0, $vr1, 15
; CHECK-NEXT:    xvreplgr2vr.b $xr1, $a0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 18
; CHECK-NEXT:    xvextrins.b $xr0, $xr1, 17
; CHECK-NEXT:    ret
entry:
  %b = extractelement <32 x i8> %a, i32 31
  %c = insertelement <32 x i8> %a, i8 %b, i32 1
  ret <32 x i8> %c
}

define <16 x i16> @insert_extract_v16i16(<16 x i16> %a) nounwind {
; CHECK-LABEL: insert_extract_v16i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvpermi.d $xr1, $xr0, 14
; CHECK-NEXT:    vpickve2gr.h $a0, $vr1, 7
; CHECK-NEXT:    xvreplgr2vr.h $xr1, $a0
; CHECK-NEXT:    xvpermi.q $xr1, $xr0, 18
; CHECK-NEXT:    xvextrins.h $xr0, $xr1, 17
; CHECK-NEXT:    ret
entry:
  %b = extractelement <16 x i16> %a, i32 15
  %c = insertelement <16 x i16> %a, i16 %b, i32 1
  ret <16 x i16> %c
}

define <8 x i32> @insert_extract_v8i32(<8 x i32> %a) nounwind {
; CHECK-LABEL: insert_extract_v8i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvpickve.w $xr1, $xr0, 7
; CHECK-NEXT:    xvinsve0.w $xr0, $xr1, 1
; CHECK-NEXT:    ret
entry:
  %b = extractelement <8 x i32> %a, i32 7
  %c = insertelement <8 x i32> %a, i32 %b, i32 1
  ret <8 x i32> %c
}


define <8 x i32> @insert_extract0_v8i32(<8 x i32> %a) nounwind {
; CHECK-LABEL: insert_extract0_v8i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvinsve0.w $xr0, $xr0, 1
; CHECK-NEXT:    ret
entry:
  %b = extractelement <8 x i32> %a, i32 0
  %c = insertelement <8 x i32> %a, i32 %b, i32 1
  ret <8 x i32> %c
}

define <8 x float> @insert_extract_v8f32(<8 x float> %a) nounwind {
; CHECK-LABEL: insert_extract_v8f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvpickve.w $xr1, $xr0, 7
; CHECK-NEXT:    xvinsve0.w $xr0, $xr1, 1
; CHECK-NEXT:    ret
entry:
  %b = extractelement <8 x float> %a, i32 7
  %c = insertelement <8 x float> %a, float %b, i32 1
  ret <8 x float> %c
}

define <4 x i64> @insert_extract_v4i64(<4 x i64> %a) nounwind {
; LA32-LABEL: insert_extract_v4i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    xvpickve.w $xr1, $xr0, 6
; LA32-NEXT:    xvpickve.w $xr2, $xr0, 7
; LA32-NEXT:    xvinsve0.w $xr0, $xr1, 2
; LA32-NEXT:    xvinsve0.w $xr0, $xr2, 3
; LA32-NEXT:    ret
;
; LA64-LABEL: insert_extract_v4i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    xvpickve.d $xr1, $xr0, 3
; LA64-NEXT:    xvinsve0.d $xr0, $xr1, 1
; LA64-NEXT:    ret
entry:
  %b = extractelement <4 x i64> %a, i32 3
  %c = insertelement <4 x i64> %a, i64 %b, i32 1
  ret <4 x i64> %c
}

define <4 x i64> @insert_extract0_v4i64(<4 x i64> %a) nounwind {
; LA32-LABEL: insert_extract0_v4i64:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    xvpickve.w $xr1, $xr0, 1
; LA32-NEXT:    xvinsve0.w $xr0, $xr0, 2
; LA32-NEXT:    xvinsve0.w $xr0, $xr1, 3
; LA32-NEXT:    ret
;
; LA64-LABEL: insert_extract0_v4i64:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    xvinsve0.d $xr0, $xr0, 1
; LA64-NEXT:    ret
entry:
  %b = extractelement <4 x i64> %a, i32 0
  %c = insertelement <4 x i64> %a, i64 %b, i32 1
  ret <4 x i64> %c
}

define <4 x double> @insert_extract_v4f64(<4 x double> %a) nounwind {
; CHECK-LABEL: insert_extract_v4f64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    xvpickve.d $xr1, $xr0, 3
; CHECK-NEXT:    xvinsve0.d $xr0, $xr1, 1
; CHECK-NEXT:    ret
entry:
  %b = extractelement <4 x double> %a, i32 3
  %c = insertelement <4 x double> %a, double %b, i32 1
  ret <4 x double> %c
}