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TheRock/compiler/amd-llvm/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/usub-sat.ll
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derek.holloway 7502bf64a4
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2026-09-02 16:34:47 -07:00

45 lines
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LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc -mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s
define <32 x i8> @xvusub_b(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: xvusub_b:
; CHECK: # %bb.0:
; CHECK-NEXT: xvssub.bu $xr0, $xr0, $xr1
; CHECK-NEXT: ret
%ret = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> %a, <32 x i8> %b)
ret <32 x i8> %ret
}
define <16 x i16> @xvusub_h(<16 x i16> %a, <16 x i16> %b) {
; CHECK-LABEL: xvusub_h:
; CHECK: # %bb.0:
; CHECK-NEXT: xvssub.hu $xr0, $xr0, $xr1
; CHECK-NEXT: ret
%ret = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
ret <16 x i16> %ret
}
define <8 x i32> @xvusub_w(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: xvusub_w:
; CHECK: # %bb.0:
; CHECK-NEXT: xvssub.wu $xr0, $xr0, $xr1
; CHECK-NEXT: ret
%ret = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %a, <8 x i32> %b)
ret <8 x i32> %ret
}
define <4 x i64> @xvusub_d(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: xvusub_d:
; CHECK: # %bb.0:
; CHECK-NEXT: xvssub.du $xr0, $xr0, $xr1
; CHECK-NEXT: ret
%ret = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %a, <4 x i64> %b)
ret <4 x i64> %ret
}
declare <32 x i8> @llvm.usub.sat.v32i8(<32 x i8>, <32 x i8>)
declare <16 x i16> @llvm.usub.sat.v16i16(<16 x i16>, <16 x i16>)
declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>)
declare <4 x i64> @llvm.usub.sat.v4i64(<4 x i64>, <4 x i64>)