derek.holloway
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105 lines
4.3 KiB
LLVM
105 lines
4.3 KiB
LLVM
; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=-relax \
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; RUN: --relocation-model=pic --code-model=medium < %s \
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; RUN: | llvm-readobj -r - | FileCheck --check-prefix=CHECK-RELOC %s
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; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=+relax \
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; RUN: --relocation-model=pic --code-model=medium < %s \
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; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK-RELOC,RELAX %s
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; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=-relax --enable-tlsdesc \
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; RUN: --relocation-model=pic --code-model=medium < %s \
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; RUN: | llvm-readobj -r - | FileCheck --check-prefix=DESC-RELOC %s
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; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=+relax --enable-tlsdesc \
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; RUN: --relocation-model=pic --code-model=medium < %s \
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; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=DESC-RELOC,DESC-RELAX %s
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;; Check relocations when disable or enable linker relaxation.
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;; This tests are also able to test for removing relax mask flags
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;; after loongarch-merge-base-offset pass because no relax relocs
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;; are emitted after being optimized by it.
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@g_e = external global i32
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@g_i = internal global i32 0
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@g_i1 = internal global i32 1
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@t_un = external thread_local global i32
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@t_ld = external thread_local(localdynamic) global i32
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@t_ie = external thread_local(initialexec) global i32
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@t_le = external thread_local(localexec) global i32
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declare void @callee1() nounwind
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declare dso_local void @callee2() nounwind
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declare dso_local void @callee3() nounwind
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; CHECK-RELOC: R_LARCH_GOT_PC_HI20 g_e 0x0
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; RELAX: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 g_e 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_PCALA_HI20 g_i 0x0
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; CHECK-RELOC-NEXT: R_LARCH_PCALA_LO12 g_i 0x0
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; CHECK-RELOC: R_LARCH_TLS_GD_PC_HI20 t_un 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 t_un 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_CALL36 __tls_get_addr 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC: R_LARCH_TLS_DESC_PC_HI20 t_un 0x0
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; DESC-RELAX: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_LO12 t_un 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_LD t_un 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_CALL t_un 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_TLS_LD_PC_HI20 t_ld 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 t_ld 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_CALL36 __tls_get_addr 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_HI20 t_ld 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_LO12 t_ld 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_LD t_ld 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_CALL t_ld 0x0
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; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_TLS_IE_PC_HI20 t_ie 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_TLS_IE_PC_LO12 t_ie 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_HI20_R t_le 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_ADD_R t_le 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_LO12_R t_le 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_PCALA_HI20 g_i1 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_PCALA_LO12 g_i1 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee1 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee2 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee3 0x0
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; RELAX-NEXT: R_LARCH_RELAX - 0x0
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;; No ALIGN reloc will emit before the first linker-relaxable instruction.
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define ptr @loader() nounwind {
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%a = load volatile i32, ptr @g_e
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%b = load volatile i32, ptr @g_i
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%c = load volatile i32, ptr @t_un
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%d = load volatile i32, ptr @t_ld
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%e = load volatile i32, ptr @t_ie
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%f = load volatile i32, ptr @t_le
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ret ptr @g_i1
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}
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;; ALIGN reloc will be emitted here.
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define void @caller() nounwind {
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call i32 @callee1()
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call i32 @callee2()
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tail call i32 @callee3()
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ret void
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}
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