derek.holloway
7502bf64a4
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412 lines
14 KiB
LLVM
412 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
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define void @and_not_combine_v16i8(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vsub.b $vr0, $vr0, $vr1
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = load <16 x i8>, ptr %a2
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%not = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%add = add <16 x i8> %not, %v2
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%and = and <16 x i8> %v0, %add
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store <16 x i8> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v8i16(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vsub.h $vr0, $vr0, $vr1
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = load <8 x i16>, ptr %a2
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%not = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%add = add <8 x i16> %not, %v2
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%and = and <8 x i16> %v0, %add
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store <8 x i16> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v4i32(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vsub.w $vr0, $vr0, $vr1
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = load <4 x i32>, ptr %a2
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%not = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
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%add = add <4 x i32> %not, %v2
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%and = and <4 x i32> %v0, %add
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store <4 x i32> %and, ptr %res
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ret void
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}
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define void @and_not_combine_v2i64(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
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; CHECK-LABEL: and_not_combine_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a3, 0
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; CHECK-NEXT: vld $vr2, $a1, 0
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; CHECK-NEXT: vsub.d $vr0, $vr0, $vr1
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr2
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = load <2 x i64>, ptr %a2
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%not = xor <2 x i64> %v1, <i64 -1, i64 -1>
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%add = add <2 x i64> %not, %v2
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%and = and <2 x i64> %v0, %add
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store <2 x i64> %and, ptr %res
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ret void
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}
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define void @pre_not_and_not_combine_v16i8(ptr %res, ptr %a, i8 %b) nounwind {
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; CHECK-LABEL: pre_not_and_not_combine_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vreplgr2vr.b $vr1, $a2
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <16 x i8>, ptr %a
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%b.not = xor i8 %b, -1
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%b.not.ele = insertelement <16 x i8> poison, i8 %b.not, i64 0
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%v1.not = shufflevector <16 x i8> %b.not.ele, <16 x i8> poison, <16 x i32> zeroinitializer
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%v0.not = xor <16 x i8> %v0, splat (i8 -1)
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%and = and <16 x i8> %v0.not, %v1.not
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store <16 x i8> %and, ptr %res
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ret void
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}
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define void @post_not_and_not_combine_v16i8(ptr %res, ptr %a, i8 %b) nounwind {
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; CHECK-LABEL: post_not_and_not_combine_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vreplgr2vr.b $vr1, $a2
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <16 x i8>, ptr %a
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%b.ele = insertelement <16 x i8> poison, i8 %b, i64 0
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%v1 = shufflevector <16 x i8> %b.ele, <16 x i8> poison, <16 x i32> zeroinitializer
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%v0.not = xor <16 x i8> %v0, splat (i8 -1)
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%v1.not = xor <16 x i8> %v1, splat (i8 -1)
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%and = and <16 x i8> %v0.not, %v1.not
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store <16 x i8> %and, ptr %res
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ret void
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}
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define void @pre_not_and_not_combine_v8i16(ptr %res, ptr %a, i16 %b) nounwind {
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; CHECK-LABEL: pre_not_and_not_combine_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vreplgr2vr.h $vr1, $a2
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <8 x i16>, ptr %a
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%b.not = xor i16 %b, -1
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%b.not.ele = insertelement <8 x i16> poison, i16 %b.not, i64 0
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%v1.not = shufflevector <8 x i16> %b.not.ele, <8 x i16> poison, <8 x i32> zeroinitializer
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%v0.not = xor <8 x i16> %v0, splat (i16 -1)
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%and = and <8 x i16> %v0.not, %v1.not
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store <8 x i16> %and, ptr %res
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ret void
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}
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define void @post_not_and_not_combine_v8i16(ptr %res, ptr %a, i16 %b) nounwind {
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; CHECK-LABEL: post_not_and_not_combine_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vreplgr2vr.h $vr1, $a2
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <8 x i16>, ptr %a
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%b.ele = insertelement <8 x i16> poison, i16 %b, i64 0
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%v1 = shufflevector <8 x i16> %b.ele, <8 x i16> poison, <8 x i32> zeroinitializer
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%v0.not = xor <8 x i16> %v0, splat (i16 -1)
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%v1.not = xor <8 x i16> %v1, splat (i16 -1)
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%and = and <8 x i16> %v0.not, %v1.not
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store <8 x i16> %and, ptr %res
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ret void
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}
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define void @pre_not_and_not_combine_v4i32(ptr %res, ptr %a, i32 %b) nounwind {
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; CHECK-LABEL: pre_not_and_not_combine_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vreplgr2vr.w $vr1, $a2
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %a
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%b.not = xor i32 %b, -1
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%b.not.ele = insertelement <4 x i32> poison, i32 %b.not, i64 0
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%v1.not = shufflevector <4 x i32> %b.not.ele, <4 x i32> poison, <4 x i32> zeroinitializer
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%v0.not = xor <4 x i32> %v0, splat (i32 -1)
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%and = and <4 x i32> %v0.not, %v1.not
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store <4 x i32> %and, ptr %res
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ret void
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}
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define void @post_not_and_not_combine_v4i32(ptr %res, ptr %a, i32 %b) nounwind {
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; CHECK-LABEL: post_not_and_not_combine_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vreplgr2vr.w $vr1, $a2
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; CHECK-NEXT: vnor.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %a
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%b.ele = insertelement <4 x i32> poison, i32 %b, i64 0
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%v1 = shufflevector <4 x i32> %b.ele, <4 x i32> poison, <4 x i32> zeroinitializer
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%v0.not = xor <4 x i32> %v0, splat (i32 -1)
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%v1.not = xor <4 x i32> %v1, splat (i32 -1)
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%and = and <4 x i32> %v0.not, %v1.not
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store <4 x i32> %and, ptr %res
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ret void
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}
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define void @pre_not_and_not_combine_v2i64(ptr %res, ptr %a, i64 %b) nounwind {
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; LA32-LABEL: pre_not_and_not_combine_v2i64:
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; LA32: # %bb.0:
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; LA32-NEXT: vld $vr0, $a1, 0
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; LA32-NEXT: nor $a1, $a3, $zero
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; LA32-NEXT: nor $a2, $a2, $zero
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; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
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; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
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; LA32-NEXT: vreplvei.d $vr1, $vr1, 0
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; LA32-NEXT: vandn.v $vr0, $vr0, $vr1
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; LA32-NEXT: vst $vr0, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: pre_not_and_not_combine_v2i64:
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; LA64: # %bb.0:
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; LA64-NEXT: vld $vr0, $a1, 0
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; LA64-NEXT: vreplgr2vr.d $vr1, $a2
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; LA64-NEXT: vnor.v $vr0, $vr0, $vr1
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; LA64-NEXT: vst $vr0, $a0, 0
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; LA64-NEXT: ret
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%v0 = load <2 x i64>, ptr %a
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%b.not = xor i64 %b, -1
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%b.not.ele = insertelement <2 x i64> poison, i64 %b.not, i64 0
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%v1.not = shufflevector <2 x i64> %b.not.ele, <2 x i64> poison, <2 x i32> zeroinitializer
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%v0.not = xor <2 x i64> %v0, splat (i64 -1)
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%and = and <2 x i64> %v0.not, %v1.not
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store <2 x i64> %and, ptr %res
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ret void
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}
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define void @post_not_and_not_combine_v2i64(ptr %res, ptr %a, i64 %b) nounwind {
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; LA32-LABEL: post_not_and_not_combine_v2i64:
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; LA32: # %bb.0:
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; LA32-NEXT: vld $vr0, $a1, 0
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; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
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; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 1
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; LA32-NEXT: vreplvei.d $vr1, $vr1, 0
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; LA32-NEXT: vnor.v $vr0, $vr0, $vr1
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; LA32-NEXT: vst $vr0, $a0, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: post_not_and_not_combine_v2i64:
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; LA64: # %bb.0:
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; LA64-NEXT: vld $vr0, $a1, 0
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; LA64-NEXT: vreplgr2vr.d $vr1, $a2
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; LA64-NEXT: vnor.v $vr0, $vr0, $vr1
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; LA64-NEXT: vst $vr0, $a0, 0
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; LA64-NEXT: ret
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%v0 = load <2 x i64>, ptr %a
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%b.ele = insertelement <2 x i64> poison, i64 %b, i64 0
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%v1 = shufflevector <2 x i64> %b.ele, <2 x i64> poison, <2 x i32> zeroinitializer
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%v0.not = xor <2 x i64> %v0, splat (i64 -1)
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%v1.not = xor <2 x i64> %v1, splat (i64 -1)
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%and = and <2 x i64> %v0.not, %v1.not
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store <2 x i64> %and, ptr %res
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ret void
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}
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define void @and_not_combine_splatimm_v16i8(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: and_not_combine_splatimm_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vnori.b $vr0, $vr0, 3
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <16 x i8>, ptr %a0
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%and = and <16 x i8> %v0, splat (i8 -4)
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%xor = xor <16 x i8> %and, splat (i8 -4)
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store <16 x i8> %xor, ptr %res
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ret void
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}
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define void @and_not_combine_splatimm_v8i16(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: and_not_combine_splatimm_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.h $vr1, -4
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <8 x i16>, ptr %a0
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%and = and <8 x i16> %v0, splat (i16 -4)
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%xor = xor <8 x i16> %and, splat (i16 -4)
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store <8 x i16> %xor, ptr %res
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ret void
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}
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define void @and_not_combine_splatimm_v4i32(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: and_not_combine_splatimm_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.w $vr1, -4
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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%v0 = load <4 x i32>, ptr %a0
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%and = and <4 x i32> %v0, splat (i32 -4)
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%xor = xor <4 x i32> %and, splat (i32 -4)
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store <4 x i32> %xor, ptr %res
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ret void
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}
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define void @and_not_combine_splatimm_v2i64(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: and_not_combine_splatimm_v2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vrepli.d $vr1, -4
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; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vst $vr0, $a0, 0
|
|
; CHECK-NEXT: ret
|
|
%v0 = load <2 x i64>, ptr %a0
|
|
%and = and <2 x i64> %v0, splat (i64 -4)
|
|
%xor = xor <2 x i64> %and, splat (i64 -4)
|
|
store <2 x i64> %xor, ptr %res
|
|
ret void
|
|
}
|
|
|
|
define void @and_or_not_combine_v16i8(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
|
|
; CHECK-LABEL: and_or_not_combine_v16i8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vld $vr0, $a0, 0
|
|
; CHECK-NEXT: vld $vr1, $a2, 0
|
|
; CHECK-NEXT: vld $vr2, $a1, 0
|
|
; CHECK-NEXT: vseq.b $vr0, $vr1, $vr0
|
|
; CHECK-NEXT: vseq.b $vr1, $vr1, $vr2
|
|
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vnori.b $vr0, $vr0, 251
|
|
; CHECK-NEXT: vst $vr0, $a3, 0
|
|
; CHECK-NEXT: ret
|
|
%a = load <16 x i8>, ptr %pa
|
|
%b = load <16 x i8>, ptr %pb
|
|
%v = load <16 x i8>, ptr %pv
|
|
%ca = icmp ne <16 x i8> %v, %a
|
|
%cb = icmp ne <16 x i8> %v, %b
|
|
%or = or <16 x i1> %ca, %cb
|
|
%ext = sext <16 x i1> %or to <16 x i8>
|
|
%and = and <16 x i8> %ext, splat (i8 4)
|
|
store <16 x i8> %and, ptr %dst
|
|
ret void
|
|
}
|
|
|
|
define void @and_or_not_combine_v8i16(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
|
|
; CHECK-LABEL: and_or_not_combine_v8i16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vld $vr0, $a0, 0
|
|
; CHECK-NEXT: vld $vr1, $a2, 0
|
|
; CHECK-NEXT: vld $vr2, $a1, 0
|
|
; CHECK-NEXT: vseq.h $vr0, $vr1, $vr0
|
|
; CHECK-NEXT: vseq.h $vr1, $vr1, $vr2
|
|
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vrepli.h $vr1, 4
|
|
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vst $vr0, $a3, 0
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x i16>, ptr %pa
|
|
%b = load <8 x i16>, ptr %pb
|
|
%v = load <8 x i16>, ptr %pv
|
|
%ca = icmp ne <8 x i16> %v, %a
|
|
%cb = icmp ne <8 x i16> %v, %b
|
|
%or = or <8 x i1> %ca, %cb
|
|
%ext = sext <8 x i1> %or to <8 x i16>
|
|
%and = and <8 x i16> %ext, splat (i16 4)
|
|
store <8 x i16> %and, ptr %dst
|
|
ret void
|
|
}
|
|
|
|
define void @and_or_not_combine_v4i32(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
|
|
; CHECK-LABEL: and_or_not_combine_v4i32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vld $vr0, $a0, 0
|
|
; CHECK-NEXT: vld $vr1, $a2, 0
|
|
; CHECK-NEXT: vld $vr2, $a1, 0
|
|
; CHECK-NEXT: vseq.w $vr0, $vr1, $vr0
|
|
; CHECK-NEXT: vseq.w $vr1, $vr1, $vr2
|
|
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vrepli.w $vr1, 4
|
|
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vst $vr0, $a3, 0
|
|
; CHECK-NEXT: ret
|
|
%a = load <4 x i32>, ptr %pa
|
|
%b = load <4 x i32>, ptr %pb
|
|
%v = load <4 x i32>, ptr %pv
|
|
%ca = icmp ne <4 x i32> %v, %a
|
|
%cb = icmp ne <4 x i32> %v, %b
|
|
%or = or <4 x i1> %ca, %cb
|
|
%ext = sext <4 x i1> %or to <4 x i32>
|
|
%and = and <4 x i32> %ext, splat (i32 4)
|
|
store <4 x i32> %and, ptr %dst
|
|
ret void
|
|
}
|
|
|
|
define void @and_or_not_combine_v2i64(ptr %pa, ptr %pb, ptr %pv, ptr %dst) nounwind {
|
|
; CHECK-LABEL: and_or_not_combine_v2i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vld $vr0, $a0, 0
|
|
; CHECK-NEXT: vld $vr1, $a2, 0
|
|
; CHECK-NEXT: vld $vr2, $a1, 0
|
|
; CHECK-NEXT: vseq.d $vr0, $vr1, $vr0
|
|
; CHECK-NEXT: vseq.d $vr1, $vr1, $vr2
|
|
; CHECK-NEXT: vand.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vrepli.d $vr1, 4
|
|
; CHECK-NEXT: vandn.v $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: vst $vr0, $a3, 0
|
|
; CHECK-NEXT: ret
|
|
%a = load <2 x i64>, ptr %pa
|
|
%b = load <2 x i64>, ptr %pb
|
|
%v = load <2 x i64>, ptr %pv
|
|
%ca = icmp ne <2 x i64> %v, %a
|
|
%cb = icmp ne <2 x i64> %v, %b
|
|
%or = or <2 x i1> %ca, %cb
|
|
%ext = sext <2 x i1> %or to <2 x i64>
|
|
%and = and <2 x i64> %ext, splat (i64 4)
|
|
store <2 x i64> %and, ptr %dst
|
|
ret void
|
|
}
|