derek.holloway
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100 lines
3.1 KiB
LLVM
100 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vdiv.b(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vdiv_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.b $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vdiv.b(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vdiv.h(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vdiv_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.h $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vdiv.h(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vdiv.w(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vdiv_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.w $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vdiv.w(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vdiv.d(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vdiv_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.d $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vdiv.d(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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declare <16 x i8> @llvm.loongarch.lsx.vdiv.bu(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vdiv_bu(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.bu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vdiv.bu(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vdiv.hu(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vdiv_hu(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.hu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vdiv.hu(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vdiv.wu(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vdiv_wu(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.wu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vdiv.wu(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vdiv.du(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vdiv_du(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vdiv_du:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vdiv.du $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vdiv.du(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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