derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
352 lines
11 KiB
LLVM
352 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
|
|
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrne.w.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftintrne_w_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrne_w_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrne.w.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrne.w.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrne.l.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftintrne_l_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrne_l_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrne.l.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrne.l.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrz.w.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftintrz_w_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrz_w_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrz.w.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrz.w.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrz.l.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftintrz_l_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrz_l_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrz.l.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrz.l.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrp.w.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftintrp_w_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrp_w_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrp.w.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrp.w.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrp.l.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftintrp_l_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrp_l_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrp.l.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrp.l.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrm.w.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftintrm_w_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrm_w_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrm.w.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrm.w.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrm.l.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftintrm_l_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrm_l_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrm.l.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrm.l.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftint.w.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftint_w_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftint_w_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftint.w.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftint.w.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftint.l.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftint_l_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftint_l_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftint.l.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftint.l.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrz.wu.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftintrz_wu_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrz_wu_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrz.wu.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrz.wu.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrz.lu.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftintrz_lu_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrz_lu_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrz.lu.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrz.lu.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftint.wu.s(<4 x float>)
|
|
|
|
define <4 x i32> @lsx_vftint_wu_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftint_wu_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftint.wu.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftint.wu.s(<4 x float> %va)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftint.lu.d(<2 x double>)
|
|
|
|
define <2 x i64> @lsx_vftint_lu_d(<2 x double> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftint_lu_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftint.lu.d $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftint.lu.d(<2 x double> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrne.w.d(<2 x double>, <2 x double>)
|
|
|
|
define <4 x i32> @lsx_vftintrne_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrne_w_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrne.w.d $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrne.w.d(<2 x double> %va, <2 x double> %vb)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrz.w.d(<2 x double>, <2 x double>)
|
|
|
|
define <4 x i32> @lsx_vftintrz_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrz_w_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrz.w.d $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrz.w.d(<2 x double> %va, <2 x double> %vb)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrp.w.d(<2 x double>, <2 x double>)
|
|
|
|
define <4 x i32> @lsx_vftintrp_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrp_w_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrp.w.d $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrp.w.d(<2 x double> %va, <2 x double> %vb)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftintrm.w.d(<2 x double>, <2 x double>)
|
|
|
|
define <4 x i32> @lsx_vftintrm_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrm_w_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrm.w.d $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftintrm.w.d(<2 x double> %va, <2 x double> %vb)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <4 x i32> @llvm.loongarch.lsx.vftint.w.d(<2 x double>, <2 x double>)
|
|
|
|
define <4 x i32> @lsx_vftint_w_d(<2 x double> %va, <2 x double> %vb) nounwind {
|
|
; CHECK-LABEL: lsx_vftint_w_d:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftint.w.d $vr0, $vr0, $vr1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <4 x i32> @llvm.loongarch.lsx.vftint.w.d(<2 x double> %va, <2 x double> %vb)
|
|
ret <4 x i32> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrnel.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrnel_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrnel_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrnel.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrnel.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrneh.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrneh_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrneh_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrneh.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrneh.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrzl.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrzl_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrzl_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrzl.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrzl.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrzh.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrzh_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrzh_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrzh.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrzh.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrpl.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrpl_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrpl_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrpl.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrpl.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrph.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrph_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrph_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrph.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrph.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrml.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrml_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrml_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrml.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrml.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintrmh.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintrmh_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintrmh_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintrmh.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintrmh.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftintl.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftintl_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftintl_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftintl.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftintl.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|
|
|
|
declare <2 x i64> @llvm.loongarch.lsx.vftinth.l.s(<4 x float>)
|
|
|
|
define <2 x i64> @lsx_vftinth_l_s(<4 x float> %va) nounwind {
|
|
; CHECK-LABEL: lsx_vftinth_l_s:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vftinth.l.s $vr0, $vr0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%res = call <2 x i64> @llvm.loongarch.lsx.vftinth.l.s(<4 x float> %va)
|
|
ret <2 x i64> %res
|
|
}
|