derek.holloway
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100 lines
3.0 KiB
LLVM
100 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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declare <16 x i8> @llvm.loongarch.lsx.vseq.b(<16 x i8>, <16 x i8>)
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define <16 x i8> @lsx_vseq_b(<16 x i8> %va, <16 x i8> %vb) nounwind {
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; CHECK-LABEL: lsx_vseq_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseq.b $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vseq.b(<16 x i8> %va, <16 x i8> %vb)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vseq.h(<8 x i16>, <8 x i16>)
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define <8 x i16> @lsx_vseq_h(<8 x i16> %va, <8 x i16> %vb) nounwind {
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; CHECK-LABEL: lsx_vseq_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseq.h $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vseq.h(<8 x i16> %va, <8 x i16> %vb)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vseq.w(<4 x i32>, <4 x i32>)
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define <4 x i32> @lsx_vseq_w(<4 x i32> %va, <4 x i32> %vb) nounwind {
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; CHECK-LABEL: lsx_vseq_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseq.w $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vseq.w(<4 x i32> %va, <4 x i32> %vb)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vseq.d(<2 x i64>, <2 x i64>)
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define <2 x i64> @lsx_vseq_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
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; CHECK-LABEL: lsx_vseq_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseq.d $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vseq.d(<2 x i64> %va, <2 x i64> %vb)
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ret <2 x i64> %res
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}
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declare <16 x i8> @llvm.loongarch.lsx.vseqi.b(<16 x i8>, i32)
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define <16 x i8> @lsx_vseqi_b(<16 x i8> %va) nounwind {
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; CHECK-LABEL: lsx_vseqi_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseqi.b $vr0, $vr0, 15
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i8> @llvm.loongarch.lsx.vseqi.b(<16 x i8> %va, i32 15)
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ret <16 x i8> %res
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}
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declare <8 x i16> @llvm.loongarch.lsx.vseqi.h(<8 x i16>, i32)
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define <8 x i16> @lsx_vseqi_h(<8 x i16> %va) nounwind {
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; CHECK-LABEL: lsx_vseqi_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseqi.h $vr0, $vr0, 15
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i16> @llvm.loongarch.lsx.vseqi.h(<8 x i16> %va, i32 15)
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ret <8 x i16> %res
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}
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declare <4 x i32> @llvm.loongarch.lsx.vseqi.w(<4 x i32>, i32)
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define <4 x i32> @lsx_vseqi_w(<4 x i32> %va) nounwind {
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; CHECK-LABEL: lsx_vseqi_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseqi.w $vr0, $vr0, -16
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i32> @llvm.loongarch.lsx.vseqi.w(<4 x i32> %va, i32 -16)
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ret <4 x i32> %res
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}
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declare <2 x i64> @llvm.loongarch.lsx.vseqi.d(<2 x i64>, i32)
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define <2 x i64> @lsx_vseqi_d(<2 x i64> %va) nounwind {
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; CHECK-LABEL: lsx_vseqi_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vseqi.d $vr0, $vr0, -16
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; CHECK-NEXT: ret
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entry:
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%res = call <2 x i64> @llvm.loongarch.lsx.vseqi.d(<2 x i64> %va, i32 -16)
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ret <2 x i64> %res
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}
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