derek.holloway
7502bf64a4
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78 lines
2.4 KiB
LLVM
78 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
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define <16 x i8> @insert_extract_v16i8(<16 x i8> %a) nounwind {
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; CHECK-LABEL: insert_extract_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextrins.b $vr0, $vr0, 31
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; CHECK-NEXT: ret
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entry:
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%b = extractelement <16 x i8> %a, i32 15
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%c = insertelement <16 x i8> %a, i8 %b, i32 1
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ret <16 x i8> %c
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}
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define <8 x i16> @insert_extract_v8i16(<8 x i16> %a) nounwind {
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; CHECK-LABEL: insert_extract_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextrins.h $vr0, $vr0, 23
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; CHECK-NEXT: ret
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entry:
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%b = extractelement <8 x i16> %a, i32 7
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%c = insertelement <8 x i16> %a, i16 %b, i32 1
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ret <8 x i16> %c
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}
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define <4 x i32> @insert_extract_v4i32(<4 x i32> %a) nounwind {
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; CHECK-LABEL: insert_extract_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextrins.w $vr0, $vr0, 19
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; CHECK-NEXT: ret
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entry:
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%b = extractelement <4 x i32> %a, i32 3
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%c = insertelement <4 x i32> %a, i32 %b, i32 1
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ret <4 x i32> %c
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}
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define <4 x float> @insert_extract_v4f32(<4 x float> %a) nounwind {
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; CHECK-LABEL: insert_extract_v4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextrins.w $vr0, $vr0, 3
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; CHECK-NEXT: ret
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entry:
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%b = extractelement <4 x float> %a, i32 3
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%c = insertelement <4 x float> %a, float %b, i32 0
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ret <4 x float> %c
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}
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define <2 x i64> @insert_extract_v2i64(<2 x i64> %a) nounwind {
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; LA32-LABEL: insert_extract_v2i64:
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; LA32: # %bb.0: # %entry
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; LA32-NEXT: vori.b $vr1, $vr0, 0
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; LA32-NEXT: vextrins.w $vr1, $vr0, 2
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; LA32-NEXT: vextrins.w $vr1, $vr0, 19
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; LA32-NEXT: vori.b $vr0, $vr1, 0
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; LA32-NEXT: ret
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;
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; LA64-LABEL: insert_extract_v2i64:
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; LA64: # %bb.0: # %entry
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; LA64-NEXT: vextrins.d $vr0, $vr0, 1
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; LA64-NEXT: ret
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entry:
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%b = extractelement <2 x i64> %a, i32 1
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%c = insertelement <2 x i64> %a, i64 %b, i32 0
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ret <2 x i64> %c
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}
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define <2 x double> @insert_extract_v2f64(<2 x double> %a) nounwind {
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; CHECK-LABEL: insert_extract_v2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextrins.d $vr0, $vr0, 1
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; CHECK-NEXT: ret
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entry:
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%b = extractelement <2 x double> %a, i32 1
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%c = insertelement <2 x double> %a, double %b, i32 0
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ret <2 x double> %c
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}
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