derek.holloway
7502bf64a4
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45 lines
1.5 KiB
LLVM
45 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
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; RUN: llc -mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
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define <16 x i8> @vuadd_b(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: vuadd_b:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsadd.bu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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%ret = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %ret
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}
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define <8 x i16> @vuadd_h(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vuadd_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsadd.hu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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%ret = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %ret
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}
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define <4 x i32> @vuadd_w(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vuadd_w:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsadd.wu $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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%ret = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %ret
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}
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define <2 x i64> @vuadd_d(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: vuadd_d:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsadd.du $vr0, $vr0, $vr1
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; CHECK-NEXT: ret
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%ret = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %ret
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}
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declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
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declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
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declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>)
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