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TheRock/compiler/amd-llvm/llvm/test/CodeGen/LoongArch/stackslot.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=loongarch64 -run-pass=machinelicm -verify-machineinstrs -o - %s \
# RUN: | FileCheck %s
## Verify the impact of isLoadFromStackSlot() on MachineLICM.
---
name: test_ld_w
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: test_ld_w
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r5 = LD_W %stack.0, 0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $r5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = ADDI_W $r5, 1
; CHECK-NEXT: BNEZ $r4, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
B %bb.1
bb.1:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
$r5 = LD_W %stack.0, 0
$r4 = ADDI_W $r5, 1
BNEZ $r4, %bb.1
B %bb.2
bb.2:
PseudoRET
...
---
name: test_fld_s
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: test_fld_s
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $f5 = FLD_S %stack.0, 0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $f5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = MOVFR2GR_S $f5
; CHECK-NEXT: BNEZ $r4, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
B %bb.1
bb.1:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
$f5 = FLD_S %stack.0, 0
$r4 = MOVFR2GR_S $f5
BNEZ $r4, %bb.1
B %bb.2
bb.2:
PseudoRET
...
---
name: test_ld_d
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: test_ld_d
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r5 = LD_D %stack.0, 0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $r5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = ADDI_D $r5, 1
; CHECK-NEXT: BNEZ $r4, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
B %bb.1
bb.1:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
$r5 = LD_D %stack.0, 0
$r4 = ADDI_D $r5, 1
BNEZ $r4, %bb.1
B %bb.2
bb.2:
PseudoRET
...
---
name: test_fld_d
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: test_fld_d
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $f5_64 = FLD_D %stack.0, 0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $f5_64
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = MOVFR2GR_D $f5_64
; CHECK-NEXT: BNEZ $r4, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
B %bb.1
bb.1:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
$f5_64 = FLD_D %stack.0, 0
$r4 = MOVFR2GR_D $f5_64
BNEZ $r4, %bb.1
B %bb.2
bb.2:
PseudoRET
...
---
name: test_vld
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: test_vld
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $vr5 = VLD %stack.0, 0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $vr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = MOVFR2GR_D $f5_64
; CHECK-NEXT: BNEZ $r4, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
B %bb.1
bb.1:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
$vr5 = VLD %stack.0, 0
$r4 = MOVFR2GR_D $f5_64
BNEZ $r4, %bb.1
B %bb.2
bb.2:
PseudoRET
...
---
name: test_xvld
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: test_xvld
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $xr5 = XVLD %stack.0, 0
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: liveins: $xr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r4 = MOVFR2GR_D $f5_64
; CHECK-NEXT: BNEZ $r4, %bb.1
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
B %bb.1
bb.1:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
$xr5 = XVLD %stack.0, 0
$r4 = MOVFR2GR_D $f5_64
BNEZ $r4, %bb.1
B %bb.2
bb.2:
PseudoRET
...