derek.holloway
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82 lines
2.3 KiB
YAML
82 lines
2.3 KiB
YAML
# RUN: llc -mtriple=nvptx -mcpu=sm_20 -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses floating point constant operands
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# correctly.
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--- |
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define float @test(float %k, i32 %i) {
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entry:
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%0 = fpext float %k to double
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%1 = fadd double %0, 3.250000e+00
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%2 = fptrunc double %1 to float
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%3 = sitofp i32 %i to float
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%4 = fadd float %3, 6.250000e+00
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%5 = fmul float %4, %2
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ret float %5
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}
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define float @test2(float %k, i32 %i) {
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entry:
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%0 = fpext float %k to double
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%1 = fadd double %0, 0x7FF8000000000000
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%2 = fptrunc double %1 to float
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%3 = sitofp i32 %i to float
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%4 = fadd float %3, 0x7FF8000000000000
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%5 = fmul float %4, %2
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ret float %5
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}
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...
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---
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name: test
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registers:
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- { id: 0, class: b32 }
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- { id: 1, class: b64 }
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- { id: 2, class: b32 }
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- { id: 3, class: b64 }
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- { id: 4, class: b32 }
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- { id: 5, class: b32 }
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- { id: 6, class: b32 }
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- { id: 7, class: b32 }
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body: |
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bb.0.entry:
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%0 = LD_i32 0, 0, 4, 2, 32, -1, &test_param_0, 0
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%1 = CVT_f64_f32 %0, 0
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%2 = LD_i32 0, 0, 4, 0, 32, -1, &test_param_1, 0
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; CHECK: %3:b64 = FADD_rnf64ri %1, double 3.250000e+00
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%3 = FADD_rnf64ri %1, double 3.250000e+00
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%4 = CVT_f32_f64 %3, 5
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%5 = CVT_f32_s32 %2, 5
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; CHECK: %6:b32 = FADD_rnf32ri %5, float 6.250000e+00
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%6 = FADD_rnf32ri %5, float 6.250000e+00, 0
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%7 = FMUL_rnf32rr %6, %4, 0
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ST_i32 %7, 0, 0, 101, 32, &func_retval0, 0 :: (store (s32), addrspace 101)
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Return
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...
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---
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name: test2
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registers:
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- { id: 0, class: b32 }
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- { id: 1, class: b64 }
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- { id: 2, class: b32 }
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- { id: 3, class: b64 }
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- { id: 4, class: b32 }
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- { id: 5, class: b32 }
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- { id: 6, class: b32 }
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- { id: 7, class: b32 }
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body: |
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bb.0.entry:
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%0 = LD_i32 0, 0, 4, 2, 32, -1, &test2_param_0, 0
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%1 = CVT_f64_f32 %0, 0
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%2 = LD_i32 0, 0, 4, 0, 32, -1, &test2_param_1, 0
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; CHECK: %3:b64 = FADD_rnf64ri %1, double +qnan
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%3 = FADD_rnf64ri %1, double 0x7FF8000000000000
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%4 = CVT_f32_f64 %3, 5
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%5 = CVT_f32_s32 %2, 5
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; CHECK: %6:b32 = FADD_rnf32ri %5, float +qnan
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%6 = FADD_rnf32ri %5, float 0x7FF8000000000000, 0
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%7 = FMUL_rnf32rr %6, %4, 0
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ST_i32 %7, 0, 0, 101, 32, &func_retval0, 0 :: (store (s32), addrspace 101)
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Return
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...
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