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102 lines
4.2 KiB
YAML
102 lines
4.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
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--- |
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define void @bswap_i32() { entry: ret void }
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define void @bswap_i64() { entry: ret void }
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...
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---
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name: bswap_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: bswap_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: $v0 = COPY [[OR2]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32R2-LABEL: name: bswap_i32
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; MIPS32R2: liveins: $a0
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
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; MIPS32R2: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_BSWAP %0
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: bswap_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: bswap_i64
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
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; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]]
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; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
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; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]
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; MIPS32: $v0 = COPY [[OR2]](s32)
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; MIPS32: $v1 = COPY [[OR5]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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; MIPS32R2-LABEL: name: bswap_i64
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; MIPS32R2: liveins: $a0, $a1
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
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; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: $v0 = COPY [[BSWAP]](s32)
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; MIPS32R2: $v1 = COPY [[BSWAP1]](s32)
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; MIPS32R2: RetRA implicit $v0, implicit $v1
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%1:_(s32) = COPY $a0
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%2:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
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%3:_(s64) = G_BSWAP %0
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%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
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$v0 = COPY %4(s32)
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$v1 = COPY %5(s32)
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RetRA implicit $v0, implicit $v1
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...
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