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56 lines
2.6 KiB
LLVM
56 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
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@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16
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@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16
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@llvm_mips_bmnzi_b_RES = global <16 x i8> zeroinitializer, align 16
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define void @llvm_mips_bmnzi_b_test() nounwind {
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entry:
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%0 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG1
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%1 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 240)
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store volatile <16 x i8> %2, ptr @llvm_mips_bmnzi_b_RES
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%3 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 15)
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store volatile <16 x i8> %3, ptr @llvm_mips_bmnzi_b_RES
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%4 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 170)
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store <16 x i8> %4, ptr @llvm_mips_bmnzi_b_RES
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ret void
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}
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; CHECK-LABEL: llvm_mips_bmnzi_b_test:
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; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)(
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; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(
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; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(
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; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]])
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; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]])
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; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]]
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; CHECK: binsli.b [[R5]], [[R3]], 3
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; CHECK: binsri.b [[R5]], [[R3]], 3
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; CHECK: bmnzi.b [[R4]], [[R3]], 170
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define void @llvm_mips_bmzi_b_test() nounwind {
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entry:
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%0 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG1
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%1 = load <16 x i8>, ptr @llvm_mips_bmnzi_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 240)
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store volatile <16 x i8> %2, ptr @llvm_mips_bmnzi_b_RES
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%3 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 15)
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store volatile <16 x i8> %3, ptr @llvm_mips_bmnzi_b_RES
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%4 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 170)
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store <16 x i8> %4, ptr @llvm_mips_bmnzi_b_RES
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ret void
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}
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; CHECK-LABEL: llvm_mips_bmzi_b_test:
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; CHECK: lw [[R0:\$[0-9]+]], %got(llvm_mips_bmnzi_b_RES)(
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; CHECK: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(
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; CHECK: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(
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; CHECK: ld.b [[R3:\$w[0-9]+]], 0([[R2]])
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; CHECK: ld.b [[R4:\$w[0-9]+]], 0([[R1]])
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; CHECK: move.v [[R5:\$w[0-9]+]], [[R4]]
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; CHECK: binsli.b [[R5]], [[R3]], 3
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; CHECK: binsri.b [[R5]], [[R3]], 3
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; bmnzi.b is the same as bmzi.b with ws and wd_in swapped
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; CHECK: bmnzi.b [[R4]], [[R3]], 170
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declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind
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declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind
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