derek.holloway
7502bf64a4
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34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=mips < %s
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; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
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; RUN: llc -mtriple=mipsel < %s
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; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
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; This test is based on an llvm-stress generated test case with seed=449609655
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; This test originally failed for MSA with a
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; "Comparison requires equal bit widths" assertion.
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; The legalizer legalized ; the <4 x i8>'s into <4 x i32>'s, then a call to
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; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt
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; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The
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; assertion occurred when trying to check the values were bitwise inverses of
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; each-other.
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;
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; It should at least successfully build.
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define void @autogen_SD449609655(i8) {
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BB:
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%Cmp = icmp ult i8 -3, %0
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br label %CF78
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CF78: ; preds = %CF81, %CF78, %BB
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%Sl31 = select i1 %Cmp, <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8> zeroinitializer
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br i1 undef, label %CF78, label %CF81
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CF81: ; preds = %CF78
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br i1 undef, label %CF78, label %CF80
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CF80: ; preds = %CF81
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%I59 = insertelement <4 x i8> %Sl31, i8 undef, i32 1
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ret void
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}
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