derek.holloway
7502bf64a4
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44 lines
1.3 KiB
LLVM
44 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s | FileCheck %s
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; RUN: %if ptxas %{ llc < %s | %ptxas-verify %}
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target triple = "nvptx64-nvidia-cuda"
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define i1 @and_ord(float %a, float %b) {
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; CHECK-LABEL: and_ord(
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; CHECK: {
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; CHECK-NEXT: .reg .pred %p<2>;
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [and_ord_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [and_ord_param_1];
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; CHECK-NEXT: setp.num.f32 %p1, %r1, %r2;
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; CHECK-NEXT: selp.b32 %r3, -1, 0, %p1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%c = fcmp ord float %a, 0.0
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%d = fcmp ord float %b, 0.0
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%e = and i1 %c, %d
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ret i1 %e
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}
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define i1 @or_uno(float %a, float %b) {
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; CHECK-LABEL: or_uno(
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; CHECK: {
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; CHECK-NEXT: .reg .pred %p<2>;
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; CHECK-NEXT: .reg .b32 %r<4>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b32 %r1, [or_uno_param_0];
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; CHECK-NEXT: ld.param.b32 %r2, [or_uno_param_1];
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; CHECK-NEXT: setp.nan.f32 %p1, %r1, %r2;
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; CHECK-NEXT: selp.b32 %r3, -1, 0, %p1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
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; CHECK-NEXT: ret;
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%c = fcmp uno float %a, 0.0
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%d = fcmp uno float %b, 0.0
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%e = or i1 %c, %d
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ret i1 %e
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}
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