derek.holloway
7502bf64a4
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85 lines
3.5 KiB
LLVM
85 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_100 -mattr=+ptx88 | FileCheck %s
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; RUN: %if ptxas-sm_100 && ptxas-isa-8.8 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -mattr=+ptx88 | %ptxas-verify -arch=sm_100 %}
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; This is testing the lowering behavior of this case from LoadStoreVectorizer/NVPTX/4x2xhalf.ll
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; where two 3xhalfs are chained together and extended to 8xhalf.
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define void @halfx3_extend_chain(ptr align 16 captures(none) %rd0) {
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; CHECK-LABEL: halfx3_extend_chain(
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; CHECK: {
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; CHECK-NEXT: .reg .b16 %rs<7>;
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; CHECK-NEXT: .reg .b32 %r<12>;
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; CHECK-NEXT: .reg .b64 %rd<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [halfx3_extend_chain_param_0];
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; CHECK-NEXT: .pragma "used_bytes_mask 0xfff";
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; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
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; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r3;
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; CHECK-NEXT: mov.b32 {_, %rs3}, %r2;
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; CHECK-NEXT: mov.b32 %r5, {%rs3, %rs1};
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; CHECK-NEXT: mov.b32 %r6, {%rs2, %rs4};
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; CHECK-NEXT: mov.b32 %r7, 0;
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; CHECK-NEXT: max.f16x2 %r8, %r2, %r7;
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; CHECK-NEXT: max.f16x2 %r9, %r1, %r7;
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; CHECK-NEXT: st.b32 [%rd1], %r9;
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; CHECK-NEXT: mov.b32 {%rs5, _}, %r8;
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; CHECK-NEXT: st.b16 [%rd1+4], %rs5;
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; CHECK-NEXT: max.f16x2 %r10, %r6, %r7;
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; CHECK-NEXT: max.f16x2 %r11, %r5, %r7;
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; CHECK-NEXT: st.b32 [%rd1+6], %r11;
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; CHECK-NEXT: mov.b32 {%rs6, _}, %r10;
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; CHECK-NEXT: st.b16 [%rd1+10], %rs6;
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; CHECK-NEXT: ret;
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%load1 = load <3 x half>, ptr %rd0, align 16
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%p1 = fcmp ogt <3 x half> %load1, zeroinitializer
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%s1 = select <3 x i1> %p1, <3 x half> %load1, <3 x half> zeroinitializer
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store <3 x half> %s1, ptr %rd0, align 16
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%in2 = getelementptr half, ptr %rd0, i64 3
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%load2 = load <3 x half>, ptr %in2, align 4
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%p2 = fcmp ogt <3 x half> %load2, zeroinitializer
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%s2 = select <3 x i1> %p2, <3 x half> %load2, <3 x half> zeroinitializer
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store <3 x half> %s2, ptr %in2, align 4
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ret void
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}
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; This disables the vectorization by reducing the alignment.
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define void @halfx3_no_align(ptr align 4 captures(none) %rd0) {
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; CHECK-LABEL: halfx3_no_align(
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; CHECK: {
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; CHECK-NEXT: .reg .b16 %rs<7>;
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; CHECK-NEXT: .reg .b32 %r<10>;
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; CHECK-NEXT: .reg .b64 %rd<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.b64 %rd1, [halfx3_no_align_param_0];
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; CHECK-NEXT: ld.b16 %rs1, [%rd1+4];
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; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
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; CHECK-NEXT: ld.b32 %r2, [%rd1];
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; CHECK-NEXT: mov.b32 %r3, 0;
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; CHECK-NEXT: max.f16x2 %r4, %r1, %r3;
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; CHECK-NEXT: max.f16x2 %r5, %r2, %r3;
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; CHECK-NEXT: st.b32 [%rd1], %r5;
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; CHECK-NEXT: mov.b32 {%rs3, _}, %r4;
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; CHECK-NEXT: st.b16 [%rd1+4], %rs3;
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; CHECK-NEXT: ld.b16 %rs4, [%rd1+10];
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; CHECK-NEXT: mov.b32 %r6, {%rs4, %rs5};
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; CHECK-NEXT: ld.b32 %r7, [%rd1+6];
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; CHECK-NEXT: max.f16x2 %r8, %r6, %r3;
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; CHECK-NEXT: max.f16x2 %r9, %r7, %r3;
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; CHECK-NEXT: st.b32 [%rd1+6], %r9;
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; CHECK-NEXT: mov.b32 {%rs6, _}, %r8;
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; CHECK-NEXT: st.b16 [%rd1+10], %rs6;
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; CHECK-NEXT: ret;
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%load1 = load <3 x half>, ptr %rd0, align 4
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%p1 = fcmp ogt <3 x half> %load1, zeroinitializer
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%s1 = select <3 x i1> %p1, <3 x half> %load1, <3 x half> zeroinitializer
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store <3 x half> %s1, ptr %rd0, align 4
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%in2 = getelementptr half, ptr %rd0, i64 3
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%load2 = load <3 x half>, ptr %in2, align 4
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%p2 = fcmp ogt <3 x half> %load2, zeroinitializer
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%s2 = select <3 x i1> %p2, <3 x half> %load2, <3 x half> zeroinitializer
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store <3 x half> %s2, ptr %in2, align 4
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ret void
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}
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