derek.holloway
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49 lines
2.0 KiB
LLVM
49 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | FileCheck --check-prefixes=CHECK %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_103a -mattr=+ptx88 | FileCheck --check-prefixes=CHECK %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_100f -mattr=+ptx88 | FileCheck --check-prefixes=CHECK %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_110f -mattr=+ptx90 | FileCheck --check-prefixes=CHECK %s
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; RUN: %if ptxas-sm_100a && ptxas-isa-8.6 %{ llc < %s -march=nvptx64 -mcpu=sm_100a -mattr=+ptx86 | %ptxas-verify -arch=sm_100a %}
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; RUN: %if ptxas-sm_103a && ptxas-isa-8.8 %{ llc < %s -march=nvptx64 -mcpu=sm_103a -mattr=+ptx88 | %ptxas-verify -arch=sm_103a %}
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; RUN: %if ptxas-sm_100f && ptxas-isa-8.8 %{ llc < %s -march=nvptx64 -mcpu=sm_100f -mattr=+ptx88 | %ptxas-verify -arch=sm_100f %}
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; RUN: %if ptxas-sm_110f && ptxas-isa-9.0 %{ llc < %s -march=nvptx64 -mcpu=sm_110f -mattr=+ptx90 | %ptxas-verify -arch=sm_110f %}
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declare void @llvm.nvvm.tcgen05.fence.before.thread.sync()
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declare void @llvm.nvvm.tcgen05.fence.after.thread.sync()
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declare void @llvm.nvvm.tcgen05.wait.ld()
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declare void @llvm.nvvm.tcgen05.wait.st()
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; CHECK-LABEL: test_tcgen05_fence
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define void @test_tcgen05_fence() {
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; CHECK-LABEL: test_tcgen05_fence(
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; CHECK: {
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; CHECK-EMPTY:
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: tcgen05.fence::before_thread_sync;
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; CHECK-NEXT: tcgen05.fence::after_thread_sync;
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; CHECK-NEXT: ret;
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call void @llvm.nvvm.tcgen05.fence.before.thread.sync()
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call void @llvm.nvvm.tcgen05.fence.after.thread.sync()
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ret void
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}
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; CHECK-LABEL: test_tcgen05_wait
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define void @test_tcgen05_wait() {
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; CHECK-LABEL: test_tcgen05_wait(
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; CHECK: {
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; CHECK-EMPTY:
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: tcgen05.wait::ld.sync.aligned;
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; CHECK-NEXT: tcgen05.wait::st.sync.aligned;
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; CHECK-NEXT: ret;
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call void @llvm.nvvm.tcgen05.wait.ld()
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call void @llvm.nvvm.tcgen05.wait.st()
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ret void
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}
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