derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1a182e2dac58879f215c0fad0f5f78c76dcafe56
TheRock/compiler/amd-llvm/llvm/test/CodeGen/PowerPC/addze.ll
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

173 lines
5.0 KiB
LLVM
Raw Blame History

; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s
define i64 @addze1(i64 %X, i64 %Z) {
; CHECK-LABEL: addze1:
; CHECK: # %bb.0:
; CHECK-NEXT: addic [[REG1:r[0-9]+]], [[REG1]], -1
; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
%cmp = icmp ne i64 %Z, 0
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @addze2(i64 %X, i64 %Z) {
; CHECK-LABEL: addze2:
; CHECK: # %bb.0:
; CHECK-NEXT: subfic [[REG1:r[0-9]+]], [[REG1]], 0
; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, 0
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @addze3(i64 %X, i64 %Z) {
; CHECK-LABEL: addze3:
; CHECK: # %bb.0:
; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768
; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
%cmp = icmp ne i64 %Z, 32768
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @addze4(i64 %X, i64 %Z) {
; CHECK-LABEL: addze4:
; CHECK: # %bb.0:
; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768
; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, 32768
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @addze5(i64 %X, i64 %Z) {
; CHECK-LABEL: addze5:
; CHECK: # %bb.0:
; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767
; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
%cmp = icmp ne i64 %Z, -32767
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @addze6(i64 %X, i64 %Z) {
; CHECK-LABEL: addze6:
; CHECK: # %bb.0:
; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767
; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, -32767
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
; element is out of range
define i64 @test1(i64 %X, i64 %Z) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr
%cmp = icmp ne i64 %Z, -32768
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @test2(i64 %X, i64 %Z) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, -32768
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @test3(i64 %X, i64 %Z) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0:
; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr
%cmp = icmp ne i64 %Z, 32769
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @test4(i64 %X, i64 %Z) {
; CHECK-LABEL: test4:
; CHECK: # %bb.0:
; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, 32769
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
; comparison of two registers
define i64 @test5(i64 %X, i64 %Y, i64 %Z) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr
%cmp = icmp ne i64 %Y, %Z
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
define i64 @test6(i64 %X, i64 %Y, i64 %Z) {
; CHECK-LABEL: test6:
; CHECK: # %bb.0:
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr
%cmp = icmp eq i64 %Y, %Z
%conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X
ret i64 %add
}
Reference in new issue View Git Blame Copy Permalink