derek.holloway
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75 lines
2.5 KiB
LLVM
75 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -mattr=+aix-shared-lib-tls-model-opt --code-model=large < %s | FileCheck %s --check-prefixes=OPT
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -mattr=+aix-small-local-dynamic-tls --code-model=large < %s | FileCheck %s --check-prefixes=SMALL
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -mattr=+aix-shared-lib-tls-model-opt -mattr=+aix-small-local-dynamic-tls \
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; RUN: --code-model=large < %s | FileCheck %s --check-prefixes=BOTH
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@VarTLSLD1 = internal thread_local(localdynamic) global i32 42, align 4
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define i32 @Single_LD(i32 %P, i32 %Q) {
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; OPT-LABEL: Single_LD:
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; OPT: # %bb.0: # %entry
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; OPT-NEXT: and 4, 3, 4
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; OPT-NEXT: addis 3, L..C0@u(2)
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; OPT-NEXT: ld 3, L..C0@l(3)
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; OPT-NEXT: cmpwi 4, -1
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; OPT-NEXT: lwzx 3, 13, 3
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; OPT-NEXT: blr
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;
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; SMALL-LABEL: Single_LD:
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; SMALL: # %bb.0: # %entry
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; SMALL-NEXT: mflr 0
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; SMALL-NEXT: stdu 1, -48(1)
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; SMALL-NEXT: and 6, 3, 4
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; SMALL-NEXT: addis 3, L..C0@u(2)
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; SMALL-NEXT: std 0, 64(1)
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; SMALL-NEXT: ld 3, L..C0@l(3)
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; SMALL-NEXT: bla .__tls_get_mod[PR]
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; SMALL-NEXT: cmpwi 6, -1
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; SMALL-NEXT: lwz 3, VarTLSLD1[TL]@ld(3)
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; SMALL-NEXT: addi 1, 1, 48
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; SMALL-NEXT: ld 0, 16(1)
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; SMALL-NEXT: mtlr 0
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; SMALL-NEXT: blr
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;
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; BOTH-LABEL: Single_LD:
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; BOTH: # %bb.0: # %entry
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; BOTH-NEXT: and 4, 3, 4
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; BOTH-NEXT: addis 3, L..C0@u(2)
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; BOTH-NEXT: ld 3, L..C0@l(3)
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; BOTH-NEXT: cmpwi 4, -1
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; BOTH-NEXT: lwzx 3, 13, 3
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; BOTH-NEXT: blr
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entry:
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%a = icmp slt i32 %P, 0
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%b = icmp slt i32 %Q, 0
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%c = and i1 %a, %b
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%tls1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1)
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%load1 = load i32, ptr %tls1, align 4
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br i1 %c, label %bb1, label %return
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bb1:
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%tls2 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @VarTLSLD1)
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%load2 = load i32, ptr %tls2, align 4
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ret i32 %load2
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return:
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ret i32 %load1
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}
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; OPT-LABEL: .toc
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; OPT-LABEL: L..C0:
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; OPT-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie
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; SMALL-LABEL: .toc
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; SMALL-LABEL: L..C0:
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; SMALL-NEXT: .tc _Renamed..5f24__TLSML[TC],_Renamed..5f24__TLSML[TC]@ml
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; SMALL-NEXT: .rename _Renamed..5f24__TLSML[TC],"_$TLSML"
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; BOTH-LABEL: .toc
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; BOTH-LABEL: L..C0:
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; BOTH-NEXT: .tc VarTLSLD1[TE],VarTLSLD1[TL]@ie
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