TheRock/compiler/amd-llvm/llvm/test/CodeGen/PowerPC/freeze-load-zext-copytoreg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s

define i32 @freeze_i8_load_multi_bb(ptr %p, i64 %len) {
; CHECK-LABEL: freeze_i8_load_multi_bb:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addi 6, 4, 1
; CHECK-NEXT:    addi 5, 4, -1
; CHECK-NEXT:    mtctr 6
; CHECK-NEXT:    li 6, 0
; CHECK-NEXT:    b .LBB0_2
; CHECK-NEXT:    .p2align 4
; CHECK-NEXT:  .LBB0_1: # %for.end
; CHECK-NEXT:    #
; CHECK-NEXT:    cmpld 6, 4
; CHECK-NEXT:    addi 6, 6, 1
; CHECK-NEXT:    beq 0, .LBB0_8
; CHECK-NEXT:  .LBB0_2: # %for.cond
; CHECK-NEXT:    # =>This Loop Header: Depth=1
; CHECK-NEXT:    # Child Loop BB0_4 Depth 2
; CHECK-NEXT:    bdz .LBB0_9
; CHECK-NEXT:  # %bb.3: # %for.body.preheader
; CHECK-NEXT:    #
; CHECK-NEXT:    lbzx 7, 3, 6
; CHECK-NEXT:    cmpd 1, 6, 5
; CHECK-NEXT:    cmplwi 7, 31
; CHECK-NEXT:    cmplwi 5, 7, 34
; CHECK-NEXT:    .p2align 5
; CHECK-NEXT:  .LBB0_4: # %for.body
; CHECK-NEXT:    # Parent Loop BB0_2 Depth=1
; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
; CHECK-NEXT:    bc 4, 1, .LBB0_1
; CHECK-NEXT:  # %bb.5: # %switch.test
; CHECK-NEXT:    #
; CHECK-NEXT:    beq 5, .LBB0_1
; CHECK-NEXT:  # %bb.6: # %switch.test
; CHECK-NEXT:    #
; CHECK-NEXT:    cmplwi 6, 7, 92
; CHECK-NEXT:    beq 6, .LBB0_1
; CHECK-NEXT:  # %bb.7: # %for.inc
; CHECK-NEXT:    #
; CHECK-NEXT:    bc 4, 6, .LBB0_4
; CHECK-NEXT:  .LBB0_8: # %ret0
; CHECK-NEXT:    li 3, 0
; CHECK-NEXT:    blr
; CHECK-NEXT:  .LBB0_9: # %ret1
; CHECK-NEXT:    li 3, 1
; CHECK-NEXT:    blr
  br label %for.cond

for.cond:
  %i = phi i64 [ 0, %0 ], [ %add, %for.end ]
  %cmp = icmp ult i64 %i, %len
  br i1 %cmp, label %for.body, label %ret1

for.body:
  %arrayidx = getelementptr inbounds i8, ptr %p, i64 %i
  %load = load i8, ptr %arrayidx, align 1
  %freeze = freeze i8 %load
  %cmp.lo = icmp ugt i8 %freeze, 31
  br i1 %cmp.lo, label %switch.test, label %for.end

switch.test:
  switch i8 %freeze, label %for.inc [
    i8 92, label %for.end
    i8 34, label %for.end
  ]

for.inc:
  %inc = add nuw i64 %i, 1
  %exitcond = icmp eq i64 %inc, %len
  br i1 %exitcond, label %ret0, label %for.body

for.end:
  %cmp.end = icmp eq i64 %i, %len
  %add = add i64 %i, 1
  br i1 %cmp.end, label %ret0, label %for.cond

ret0:
  ret i32 0

ret1:
  ret i32 1
}

define i32 @freeze_i8_load_loop(ptr %p, i32 %n) {
; CHECK-LABEL: freeze_i8_load_loop:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpwi 4, 1
; CHECK-NEXT:    li 5, 1
; CHECK-NEXT:    lbz 3, 0(3)
; CHECK-NEXT:    iselgt 4, 4, 5
; CHECK-NEXT:    mullw 3, 4, 3
; CHECK-NEXT:    clrldi 4, 4, 32
; CHECK-NEXT:    mtctr 4
; CHECK-NEXT:    .p2align 4
; CHECK-NEXT:  .LBB1_1: # %loop
; CHECK-NEXT:    #
; CHECK-NEXT:    bdnz .LBB1_1
; CHECK-NEXT:  # %bb.2: # %exit
; CHECK-NEXT:    blr
  %load = load i8, ptr %p
  %freeze = freeze i8 %load
  %zext = zext i8 %freeze to i32
  br label %loop

loop:
  %acc = phi i32 [ 0, %0 ], [ %sum, %loop ]
  %i = phi i32 [ 0, %0 ], [ %inc, %loop ]
  %sum = add i32 %acc, %zext
  %inc = add i32 %i, 1
  %cmp = icmp slt i32 %inc, %n
  br i1 %cmp, label %loop, label %exit

exit:
  ret i32 %sum
}

define i32 @freeze_i16_load_cross_bb(ptr %p, i1 %cond) {
; CHECK-LABEL: freeze_i16_load_cross_bb:
; CHECK:       # %bb.0:
; CHECK-NEXT:    andi. 4, 4, 1
; CHECK-NEXT:    bc 4, 1, .LBB2_2
; CHECK-NEXT:  # %bb.1: # %then
; CHECK-NEXT:    lhz 3, 0(3)
; CHECK-NEXT:    blr
; CHECK-NEXT:  .LBB2_2: # %else
; CHECK-NEXT:    li 3, 0
; CHECK-NEXT:    blr
  %load = load i16, ptr %p
  %freeze = freeze i16 %load
  br i1 %cond, label %then, label %else

then:
  %zext = zext i16 %freeze to i32
  ret i32 %zext

else:
  ret i32 0
}

define i32 @freeze_non_load_cross_bb(i8 %val, i1 %cond) {
; CHECK-LABEL: freeze_non_load_cross_bb:
; CHECK:       # %bb.0:
; CHECK-NEXT:    andi. 4, 4, 1
; CHECK-NEXT:    bc 4, 1, .LBB3_2
; CHECK-NEXT:  # %bb.1: # %then
; CHECK-NEXT:    clrldi 3, 3, 56
; CHECK-NEXT:    blr
; CHECK-NEXT:  .LBB3_2: # %else
; CHECK-NEXT:    li 3, 0
; CHECK-NEXT:    blr
  %freeze = freeze i8 %val
  br i1 %cond, label %then, label %else

then:
  %zext = zext i8 %freeze to i32
  ret i32 %zext

else:
  ret i32 0
}