derek.holloway
7502bf64a4
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21 lines
819 B
LLVM
21 lines
819 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test vector sign extend builtins.
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declare <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64>) nounwind readnone
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define <1 x i128> @test_vextsd2q(<2 x i64> %x) nounwind readnone {
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; CHECK-LABEL: test_vextsd2q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vextsd2q v2, v2
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; CHECK-NEXT: blr
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%tmp = tail call <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64> %x)
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ret <1 x i128> %tmp
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}
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