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TheRock/compiler/amd-llvm/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

78 lines
2.8 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind
define void @foo(ptr nocapture %r1, ptr nocapture %r2, ptr nocapture %r3, ptr nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 {
; Make sure that we don't schedule all of the isels together, they should be
; intermixed with the adds because each isel starts a new dispatch group.
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi 7, 0
; CHECK-NEXT: addi 7, 8, 1
; CHECK-NEXT: iseleq 9, 9, 8
; CHECK-NEXT: stw 9, 0(3)
; CHECK-NEXT: addi 3, 10, -2
; CHECK-NEXT: iseleq 9, 10, 8
; CHECK-NEXT: iseleq 3, 3, 7
; CHECK-NEXT: stw 9, 0(4)
; CHECK-NEXT: addi 4, 10, -5
; CHECK-NEXT: stw 3, 0(5)
; CHECK-NEXT: addi 3, 8, 3
; CHECK-NEXT: iseleq 3, 4, 3
; CHECK-NEXT: stw 3, 0(6)
; CHECK-NEXT: blr
;
; CHECK-NO-ISEL-LABEL: foo:
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: cmplwi 7, 0
; CHECK-NO-ISEL-NEXT: mr 7, 8
; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: mr 7, 9
; CHECK-NO-ISEL-NEXT: .LBB0_2: # %entry
; CHECK-NO-ISEL-NEXT: stw 7, 0(3)
; CHECK-NO-ISEL-NEXT: mr 3, 8
; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_4
; CHECK-NO-ISEL-NEXT: # %bb.3: # %entry
; CHECK-NO-ISEL-NEXT: mr 3, 10
; CHECK-NO-ISEL-NEXT: .LBB0_4: # %entry
; CHECK-NO-ISEL-NEXT: stw 3, 0(4)
; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_7
; CHECK-NO-ISEL-NEXT: # %bb.5: # %entry
; CHECK-NO-ISEL-NEXT: addi 3, 10, -2
; CHECK-NO-ISEL-NEXT: stw 3, 0(5)
; CHECK-NO-ISEL-NEXT: beq 0, .LBB0_8
; CHECK-NO-ISEL-NEXT: .LBB0_6:
; CHECK-NO-ISEL-NEXT: addi 3, 8, 3
; CHECK-NO-ISEL-NEXT: stw 3, 0(6)
; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL-NEXT: .LBB0_7:
; CHECK-NO-ISEL-NEXT: addi 3, 8, 1
; CHECK-NO-ISEL-NEXT: stw 3, 0(5)
; CHECK-NO-ISEL-NEXT: bne 0, .LBB0_6
; CHECK-NO-ISEL-NEXT: .LBB0_8: # %entry
; CHECK-NO-ISEL-NEXT: addi 3, 10, -5
; CHECK-NO-ISEL-NEXT: stw 3, 0(6)
; CHECK-NO-ISEL-NEXT: blr
entry:
%tobool = icmp ne i32 %a, 0
%cond = select i1 %tobool, i32 %b, i32 %c
store i32 %cond, ptr %r1, align 4
%cond5 = select i1 %tobool, i32 %b, i32 %d
store i32 %cond5, ptr %r2, align 4
%add = add nsw i32 %b, 1
%sub = add nsw i32 %d, -2
%cond10 = select i1 %tobool, i32 %add, i32 %sub
store i32 %cond10, ptr %r3, align 4
%add13 = add nsw i32 %b, 3
%sub15 = add nsw i32 %d, -5
%cond17 = select i1 %tobool, i32 %add13, i32 %sub15
store i32 %cond17, ptr %r4, align 4
ret void
}
attributes #0 = { nounwind }