derek.holloway
7502bf64a4
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95 lines
2.8 KiB
LLVM
95 lines
2.8 KiB
LLVM
; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck --check-prefix=CHECK-LNX %s
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; RUN: llc -enable-ppc-gen-scalar-mass -verify-machineinstrs -O3 -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK-AIX %s
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declare float @llvm.pow.f32 (float, float);
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declare double @llvm.pow.f64 (double, double);
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; afn flag powf with 0.25
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define float @llvmintr_powf_f32_afn025(float %a) {
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; CHECK-LNX-LABEL: llvmintr_powf_f32_afn025:
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; CHECK-LNX: bl __xl_powf
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; CHECK-LNX: blr
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;
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; CHECK-AIX-LABEL: llvmintr_powf_f32_afn025:
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; CHECK-AIX: bl .__xl_powf[PR]
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; CHECK-AIX: blr
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entry:
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%call = tail call afn float @llvm.pow.f32(float %a, float 2.500000e-01)
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ret float %call
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}
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; afn flag pow with 0.25
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define double @llvmintr_pow_f64_afn025(double %a) {
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; CHECK-LNX-LABEL: llvmintr_pow_f64_afn025:
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; CHECK-LNX: bl __xl_pow
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; CHECK-LNX: blr
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;
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; CHECK-AIX-LABEL: llvmintr_pow_f64_afn025:
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; CHECK-AIX: bl .__xl_pow[PR]
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; CHECK-AIX: blr
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entry:
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%call = tail call afn double @llvm.pow.f64(double %a, double 2.500000e-01)
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ret double %call
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}
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; afn flag powf with 0.75
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define float @llvmintr_powf_f32_afn075(float %a) {
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; CHECK-LNX-LABEL: llvmintr_powf_f32_afn075:
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; CHECK-LNX: bl __xl_powf
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; CHECK-LNX: blr
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;
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; CHECK-AIX-LABEL: llvmintr_powf_f32_afn075:
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; CHECK-AIX: # %bb.0: # %entry
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; CHECK-AIX: bl .__xl_powf[PR]
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; CHECK-AIX: blr
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entry:
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%call = tail call afn float @llvm.pow.f32(float %a, float 7.500000e-01)
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ret float %call
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}
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; afn flag pow with 0.75
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define double @llvmintr_pow_f64_afn075(double %a) {
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; CHECK-LNX-LABEL: llvmintr_pow_f64_afn075:
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; CHECK-LNX: bl __xl_pow
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; CHECK-LNX: blr
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;
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; CHECK-AIX-LABEL: llvmintr_pow_f64_afn075:
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; CHECK-AIX: bl .__xl_pow[PR]
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; CHECK-AIX: blr
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entry:
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%call = tail call afn double @llvm.pow.f64(double %a, double 7.500000e-01)
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ret double %call
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}
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; afn flag powf with 0.50
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define float @llvmintr_powf_f32_afn050(float %a) {
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; CHECK-LNX-LABEL: llvmintr_powf_f32_afn050:
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; CHECK-LNX: # %bb.0: # %entry
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; CHECK-LNX: bl __xl_powf
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; CHECK-LNX: blr
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;
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; CHECK-AIX-LABEL: llvmintr_powf_f32_afn050:
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; CHECK-AIX: # %bb.0: # %entry
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; CHECK-AIX: bl .__xl_powf[PR]
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; CHECK-AIX: blr
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entry:
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%call = tail call afn float @llvm.pow.f32(float %a, float 5.000000e-01)
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ret float %call
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}
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; afn flag pow with 0.50
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define double @llvmintr_pow_f64_afn050(double %a) {
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; CHECK-LNX-LABEL: llvmintr_pow_f64_afn050:
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; CHECK-LNX: # %bb.0: # %entry
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; CHECK-LNX: bl __xl_pow
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; CHECK-LNX: blr
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;
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; CHECK-AIX-LABEL: llvmintr_pow_f64_afn050:
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; CHECK-AIX: # %bb.0: # %entry
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; CHECK-AIX: bl .__xl_pow[PR]
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; CHECK-AIX: blr
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entry:
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%call = tail call afn double @llvm.pow.f64(double %a, double 5.000000e-01)
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ret double %call
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}
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