derek.holloway
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139 lines
3.8 KiB
YAML
139 lines
3.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -run-pass=riscv-prelegalizer-combiner -mtriple riscv64 %s -o - | FileCheck %s --check-prefix=RV64
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---
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name: nneg_zext
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body: |
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bb.0:
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; RV64-LABEL: name: nneg_zext
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; RV64: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
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; RV64-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
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; RV64-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $x10
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%2:_(s32) = G_TRUNC %0
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%3:_(s64) = nneg G_ZEXT %2
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$x10 = COPY %3(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_shl
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_shl
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_SHL %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_lshr
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_lshr
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_LSHR %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_ashr
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_ashr
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_ASHR %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_sdiv
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_sdiv
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_SDIV %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_udiv
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_udiv
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_UDIV %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_srem
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_srem
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_SREM %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_urem
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_urem
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_UREM %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: binop_left_to_zero_mul
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body: |
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bb.0:
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; RV64-LABEL: name: binop_left_to_zero_mul
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; RV64: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; RV64-NEXT: $x10 = COPY [[C]](s64)
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; RV64-NEXT: PseudoRET implicit $x10
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%0:_(s64) = G_CONSTANT i64 0
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%1:_(s64) = COPY $x10
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%2:_(s64) = G_MUL %0, %1
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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