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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

1845 lines
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel -mattr=+d \
; RUN: -target-abi=ilp32d \
; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel -mattr=+d \
; RUN: -target-abi=lp64d \
; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -global-isel \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -global-isel \
; RUN: | FileCheck -check-prefix=RV64I %s
define double @sqrt_f64(double %a) nounwind {
; CHECKIFD-LABEL: sqrt_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fsqrt.d fa0, fa0
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: sqrt_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call sqrt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: sqrt_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call sqrt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.sqrt.f64(double %a)
ret double %1
}
define double @powi_f64(double %a, i32 %b) nounwind {
; RV32IFD-LABEL: powi_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __powidf2
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: powi_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: sext.w a0, a0
; RV64IFD-NEXT: call __powidf2
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: powi_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __powidf2
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: powi_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __powidf2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.powi.f64.i32(double %a, i32 %b)
ret double %1
}
define double @sin_f64(double %a) nounwind {
; RV32IFD-LABEL: sin_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call sin
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: sin_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call sin
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: sin_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call sin
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: sin_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call sin
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.sin.f64(double %a)
ret double %1
}
define double @cos_f64(double %a) nounwind {
; RV32IFD-LABEL: cos_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call cos
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: cos_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call cos
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: cos_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call cos
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: cos_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call cos
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.cos.f64(double %a)
ret double %1
}
; The sin+cos combination results in an FSINCOS SelectionDAG node.
define double @sincos_f64(double %a) nounwind {
; RV32IFD-LABEL: sincos_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: call sin
; RV32IFD-NEXT: fmv.d fs1, fa0
; RV32IFD-NEXT: fmv.d fa0, fs0
; RV32IFD-NEXT: call cos
; RV32IFD-NEXT: fadd.d fa0, fs1, fa0
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: sincos_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: call sin
; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: fmv.d fa0, fs0
; RV64IFD-NEXT: call cos
; RV64IFD-NEXT: fadd.d fa0, fs1, fa0
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 16(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: sincos_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: call sin
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call cos
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __adddf3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: sincos_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: call sin
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call cos
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = call double @llvm.sin.f64(double %a)
%2 = call double @llvm.cos.f64(double %a)
%3 = fadd double %1, %2
ret double %3
}
define double @pow_f64(double %a, double %b) nounwind {
; RV32IFD-LABEL: pow_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call pow
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: pow_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call pow
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: pow_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call pow
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: pow_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call pow
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.pow.f64(double %a, double %b)
ret double %1
}
define double @exp_f64(double %a) nounwind {
; RV32IFD-LABEL: exp_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call exp
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: exp_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call exp
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: exp_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call exp
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: exp_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call exp
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.exp.f64(double %a)
ret double %1
}
define double @exp2_f64(double %a) nounwind {
; RV32IFD-LABEL: exp2_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call exp2
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: exp2_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call exp2
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: exp2_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call exp2
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: exp2_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call exp2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.exp2.f64(double %a)
ret double %1
}
define double @exp10_f64(double %a) nounwind {
; RV32IFD-LABEL: exp10_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call exp10
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: exp10_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call exp10
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: exp10_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call exp10
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: exp10_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call exp10
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.exp10.f64(double %a)
ret double %1
}
define double @log_f64(double %a) nounwind {
; RV32IFD-LABEL: log_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call log
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: log_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call log
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: log_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call log
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: log_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call log
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.log.f64(double %a)
ret double %1
}
define double @log10_f64(double %a) nounwind {
; RV32IFD-LABEL: log10_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call log10
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: log10_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call log10
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: log10_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call log10
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: log10_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call log10
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.log10.f64(double %a)
ret double %1
}
define double @log2_f64(double %a) nounwind {
; RV32IFD-LABEL: log2_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call log2
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: log2_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call log2
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: log2_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call log2
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: log2_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call log2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.log2.f64(double %a)
ret double %1
}
define double @fma_f64(double %a, double %b, double %c) nounwind {
; CHECKIFD-LABEL: fma_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fma_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fma
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fma_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fma
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %1
}
define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
; CHECKIFD-LABEL: fmuladd_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmadd.d fa0, fa0, fa1, fa2
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fmuladd_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a4
; RV32I-NEXT: mv s1, a5
; RV32I-NEXT: call __muldf3
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __adddf3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fmuladd_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: call __muldf3
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
ret double %1
}
define double @fabs_f64(double %a) nounwind {
; CHECKIFD-LABEL: fabs_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fabs.d fa0, fa0
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fabs_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fabs_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%1 = call double @llvm.fabs.f64(double %a)
ret double %1
}
define double @minnum_f64(double %a, double %b) nounwind {
; CHECKIFD-LABEL: minnum_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmin.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: minnum_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fmin
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: minnum_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmin
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.minnum.f64(double %a, double %b)
ret double %1
}
define double @maxnum_f64(double %a, double %b) nounwind {
; CHECKIFD-LABEL: maxnum_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fmax.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: maxnum_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fmax
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: maxnum_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmax
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.maxnum.f64(double %a, double %b)
ret double %1
}
define double @copysign_f64(double %a, double %b) nounwind {
; CHECKIFD-LABEL: copysign_f64:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fsgnj.d fa0, fa0, fa1
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: copysign_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: copysign_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a1, a1, 63
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
ret double %1
}
define double @floor_f64(double %a) nounwind {
; RV32IFD-LABEL: floor_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: floor_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call floor
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: floor_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call floor
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: floor_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call floor
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.floor.f64(double %a)
ret double %1
}
define double @ceil_f64(double %a) nounwind {
; RV32IFD-LABEL: ceil_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call ceil
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: ceil_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call ceil
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: ceil_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call ceil
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: ceil_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call ceil
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.ceil.f64(double %a)
ret double %1
}
define double @trunc_f64(double %a) nounwind {
; RV32IFD-LABEL: trunc_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call trunc
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: trunc_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call trunc
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: trunc_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call trunc
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: trunc_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call trunc
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.trunc.f64(double %a)
ret double %1
}
define double @rint_f64(double %a) nounwind {
; RV32IFD-LABEL: rint_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call rint
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: rint_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call rint
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: rint_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call rint
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: rint_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call rint
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.rint.f64(double %a)
ret double %1
}
define double @nearbyint_f64(double %a) nounwind {
; RV32IFD-LABEL: nearbyint_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call nearbyint
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: nearbyint_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call nearbyint
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: nearbyint_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call nearbyint
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: nearbyint_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call nearbyint
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.nearbyint.f64(double %a)
ret double %1
}
define double @round_f64(double %a) nounwind {
; RV32IFD-LABEL: round_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call round
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: round_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call round
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: round_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call round
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: round_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call round
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.round.f64(double %a)
ret double %1
}
define double @roundeven_f64(double %a) nounwind {
; RV32IFD-LABEL: roundeven_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call roundeven
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: roundeven_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call roundeven
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: roundeven_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call roundeven
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: roundeven_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call roundeven
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.roundeven.f64(double %a)
ret double %1
}
define i1 @isnan_d_fpclass(double %x) {
; CHECKIFD-LABEL: isnan_d_fpclass:
; CHECKIFD: # %bb.0:
; CHECKIFD-NEXT: fclass.d a0, fa0
; CHECKIFD-NEXT: andi a0, a0, 768
; CHECKIFD-NEXT: snez a0, a0
; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: isnan_d_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524032
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: beq a1, a2, .LBB25_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a2, a1
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB25_2:
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: isnan_d_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 2047
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: slli a1, a1, 52
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
ret i1 %1
}
define i1 @isnan_q_fpclass(fp128 %x) {
; RV32IFD-LABEL: isnan_q_fpclass:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lw a3, 4(a0)
; RV32IFD-NEXT: lw a2, 12(a0)
; RV32IFD-NEXT: lw a1, 8(a0)
; RV32IFD-NEXT: slli a2, a2, 1
; RV32IFD-NEXT: beqz a3, .LBB26_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: snez a0, a3
; RV32IFD-NEXT: j .LBB26_3
; RV32IFD-NEXT: .LBB26_2:
; RV32IFD-NEXT: lw a0, 0(a0)
; RV32IFD-NEXT: snez a0, a0
; RV32IFD-NEXT: .LBB26_3:
; RV32IFD-NEXT: lui a3, 524272
; RV32IFD-NEXT: srli a2, a2, 1
; RV32IFD-NEXT: bnez a1, .LBB26_6
; RV32IFD-NEXT: # %bb.4:
; RV32IFD-NEXT: bne a2, a3, .LBB26_7
; RV32IFD-NEXT: .LBB26_5:
; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB26_6:
; RV32IFD-NEXT: snez a0, a1
; RV32IFD-NEXT: beq a2, a3, .LBB26_5
; RV32IFD-NEXT: .LBB26_7:
; RV32IFD-NEXT: sltu a0, a3, a2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: isnan_q_fpclass:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a2, 32767
; RV64IFD-NEXT: slli a3, a1, 1
; RV64IFD-NEXT: slli a1, a2, 36
; RV64IFD-NEXT: srli a2, a3, 1
; RV64IFD-NEXT: beq a2, a1, .LBB26_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: sltu a0, a1, a2
; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB26_2:
; RV64IFD-NEXT: snez a0, a0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: isnan_q_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: lw a1, 8(a0)
; RV32I-NEXT: slli a2, a2, 1
; RV32I-NEXT: beqz a3, .LBB26_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: snez a0, a3
; RV32I-NEXT: j .LBB26_3
; RV32I-NEXT: .LBB26_2:
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: .LBB26_3:
; RV32I-NEXT: lui a3, 524272
; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: bnez a1, .LBB26_6
; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: bne a2, a3, .LBB26_7
; RV32I-NEXT: .LBB26_5:
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB26_6:
; RV32I-NEXT: snez a0, a1
; RV32I-NEXT: beq a2, a3, .LBB26_5
; RV32I-NEXT: .LBB26_7:
; RV32I-NEXT: sltu a0, a3, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: isnan_q_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 32767
; RV64I-NEXT: slli a3, a1, 1
; RV64I-NEXT: slli a1, a2, 36
; RV64I-NEXT: srli a2, a3, 1
; RV64I-NEXT: beq a2, a1, .LBB26_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sltu a0, a1, a2
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB26_2:
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3) ; nan
ret i1 %1
}
define i1 @iszero_q_fpclass(fp128 %x) {
; RV32IFD-LABEL: iszero_q_fpclass:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lw a1, 0(a0)
; RV32IFD-NEXT: lw a2, 4(a0)
; RV32IFD-NEXT: lw a3, 8(a0)
; RV32IFD-NEXT: lw a0, 12(a0)
; RV32IFD-NEXT: or a1, a1, a2
; RV32IFD-NEXT: or a0, a3, a0
; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: iszero_q_fpclass:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: iszero_q_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a2, 4(a0)
; RV32I-NEXT: lw a3, 8(a0)
; RV32I-NEXT: lw a0, 12(a0)
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: iszero_q_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 64) ; positive zero
ret i1 %1
}
define i1 @isinf_q_fpclass(fp128 %x) {
; RV32IFD-LABEL: isinf_q_fpclass:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lw a1, 0(a0)
; RV32IFD-NEXT: lw a2, 12(a0)
; RV32IFD-NEXT: lw a4, 4(a0)
; RV32IFD-NEXT: lw a3, 8(a0)
; RV32IFD-NEXT: lui a5, 1048560
; RV32IFD-NEXT: slli a6, a2, 1
; RV32IFD-NEXT: sltiu a0, a1, 0
; RV32IFD-NEXT: sltu a1, a4, a4
; RV32IFD-NEXT: seqz a7, a4
; RV32IFD-NEXT: and a7, a7, a0
; RV32IFD-NEXT: or a1, a1, a7
; RV32IFD-NEXT: seqz a7, a3
; RV32IFD-NEXT: and a7, a7, a1
; RV32IFD-NEXT: sub a1, a3, a1
; RV32IFD-NEXT: sltu t0, a3, a3
; RV32IFD-NEXT: srli a6, a6, 1
; RV32IFD-NEXT: sub a4, a4, a0
; RV32IFD-NEXT: xor a3, a2, a6
; RV32IFD-NEXT: or a2, t0, a7
; RV32IFD-NEXT: add a5, a6, a5
; RV32IFD-NEXT: beqz a4, .LBB28_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: sltiu a0, a4, 0
; RV32IFD-NEXT: .LBB28_2:
; RV32IFD-NEXT: mv a4, a3
; RV32IFD-NEXT: sub a2, a5, a2
; RV32IFD-NEXT: lui a3, 524256
; RV32IFD-NEXT: beqz a1, .LBB28_4
; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: sltiu a0, a1, 0
; RV32IFD-NEXT: .LBB28_4:
; RV32IFD-NEXT: snez a1, a4
; RV32IFD-NEXT: beq a2, a3, .LBB28_6
; RV32IFD-NEXT: # %bb.5:
; RV32IFD-NEXT: sltu a0, a2, a3
; RV32IFD-NEXT: .LBB28_6:
; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: isinf_q_fpclass:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slli a2, a1, 1
; RV64IFD-NEXT: li a3, 1
; RV64IFD-NEXT: sltiu a0, a0, 0
; RV64IFD-NEXT: srli a2, a2, 1
; RV64IFD-NEXT: slli a3, a3, 48
; RV64IFD-NEXT: xor a1, a1, a2
; RV64IFD-NEXT: sub a2, a2, a3
; RV64IFD-NEXT: lui a3, 16383
; RV64IFD-NEXT: mv a1, a1
; RV64IFD-NEXT: sub a2, a2, a0
; RV64IFD-NEXT: slli a3, a3, 37
; RV64IFD-NEXT: snez a1, a1
; RV64IFD-NEXT: beq a2, a3, .LBB28_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: sltu a0, a2, a3
; RV64IFD-NEXT: .LBB28_2:
; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: isinf_q_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: lw a4, 4(a0)
; RV32I-NEXT: lw a3, 8(a0)
; RV32I-NEXT: lui a5, 1048560
; RV32I-NEXT: slli a6, a2, 1
; RV32I-NEXT: sltiu a0, a1, 0
; RV32I-NEXT: sltu a1, a4, a4
; RV32I-NEXT: seqz a7, a4
; RV32I-NEXT: and a7, a7, a0
; RV32I-NEXT: or a1, a1, a7
; RV32I-NEXT: seqz a7, a3
; RV32I-NEXT: and a7, a7, a1
; RV32I-NEXT: sub a1, a3, a1
; RV32I-NEXT: sltu t0, a3, a3
; RV32I-NEXT: srli a6, a6, 1
; RV32I-NEXT: sub a4, a4, a0
; RV32I-NEXT: xor a3, a2, a6
; RV32I-NEXT: or a2, t0, a7
; RV32I-NEXT: add a5, a6, a5
; RV32I-NEXT: beqz a4, .LBB28_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltiu a0, a4, 0
; RV32I-NEXT: .LBB28_2:
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: sub a2, a5, a2
; RV32I-NEXT: lui a3, 524256
; RV32I-NEXT: beqz a1, .LBB28_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltiu a0, a1, 0
; RV32I-NEXT: .LBB28_4:
; RV32I-NEXT: snez a1, a4
; RV32I-NEXT: beq a2, a3, .LBB28_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: sltu a0, a2, a3
; RV32I-NEXT: .LBB28_6:
; RV32I-NEXT: xori a1, a1, 1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: isinf_q_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a1, 1
; RV64I-NEXT: li a3, 1
; RV64I-NEXT: sltiu a0, a0, 0
; RV64I-NEXT: srli a2, a2, 1
; RV64I-NEXT: slli a3, a3, 48
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: sub a2, a2, a3
; RV64I-NEXT: lui a3, 16383
; RV64I-NEXT: mv a1, a1
; RV64I-NEXT: sub a2, a2, a0
; RV64I-NEXT: slli a3, a3, 37
; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: beq a2, a3, .LBB28_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sltu a0, a2, a3
; RV64I-NEXT: .LBB28_2:
; RV64I-NEXT: xori a1, a1, 1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 256) ; positive infinity
ret i1 %1
}
define i1 @isinf_or_zero_q_fpclass(fp128 %x) {
; RV32IFD-LABEL: isinf_or_zero_q_fpclass:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: lw a3, 0(a0)
; RV32IFD-NEXT: lw a4, 12(a0)
; RV32IFD-NEXT: lw a5, 4(a0)
; RV32IFD-NEXT: lw a6, 8(a0)
; RV32IFD-NEXT: lui a7, 1048560
; RV32IFD-NEXT: slli t0, a4, 1
; RV32IFD-NEXT: or a1, a3, a5
; RV32IFD-NEXT: or a2, a6, a4
; RV32IFD-NEXT: sltiu a0, a3, 0
; RV32IFD-NEXT: sltu a3, a5, a5
; RV32IFD-NEXT: seqz t1, a5
; RV32IFD-NEXT: and t1, t1, a0
; RV32IFD-NEXT: or a3, a3, t1
; RV32IFD-NEXT: seqz t1, a6
; RV32IFD-NEXT: and t1, t1, a3
; RV32IFD-NEXT: sub a3, a6, a3
; RV32IFD-NEXT: sltu t2, a6, a6
; RV32IFD-NEXT: srli t0, t0, 1
; RV32IFD-NEXT: sub a5, a5, a0
; RV32IFD-NEXT: xor a6, a4, t0
; RV32IFD-NEXT: or a4, t2, t1
; RV32IFD-NEXT: add a7, t0, a7
; RV32IFD-NEXT: beqz a5, .LBB29_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: sltiu a0, a5, 0
; RV32IFD-NEXT: .LBB29_2:
; RV32IFD-NEXT: mv a6, a6
; RV32IFD-NEXT: or a5, a1, a2
; RV32IFD-NEXT: sub a1, a7, a4
; RV32IFD-NEXT: lui a2, 524256
; RV32IFD-NEXT: beqz a3, .LBB29_4
; RV32IFD-NEXT: # %bb.3:
; RV32IFD-NEXT: sltiu a0, a3, 0
; RV32IFD-NEXT: .LBB29_4:
; RV32IFD-NEXT: snez a4, a6
; RV32IFD-NEXT: seqz a3, a5
; RV32IFD-NEXT: beq a1, a2, .LBB29_6
; RV32IFD-NEXT: # %bb.5:
; RV32IFD-NEXT: sltu a0, a1, a2
; RV32IFD-NEXT: .LBB29_6:
; RV32IFD-NEXT: xori a1, a4, 1
; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: or a0, a3, a0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: isinf_or_zero_q_fpclass:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: slli a2, a1, 1
; RV64IFD-NEXT: or a5, a0, a1
; RV64IFD-NEXT: li a3, 1
; RV64IFD-NEXT: sltiu a0, a0, 0
; RV64IFD-NEXT: srli a2, a2, 1
; RV64IFD-NEXT: slli a3, a3, 48
; RV64IFD-NEXT: xor a1, a1, a2
; RV64IFD-NEXT: sub a2, a2, a3
; RV64IFD-NEXT: lui a3, 16383
; RV64IFD-NEXT: slli a3, a3, 37
; RV64IFD-NEXT: mv a1, a1
; RV64IFD-NEXT: sub a4, a2, a0
; RV64IFD-NEXT: snez a2, a1
; RV64IFD-NEXT: seqz a1, a5
; RV64IFD-NEXT: beq a4, a3, .LBB29_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: sltu a0, a4, a3
; RV64IFD-NEXT: .LBB29_2:
; RV64IFD-NEXT: xori a2, a2, 1
; RV64IFD-NEXT: and a0, a0, a2
; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: isinf_or_zero_q_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: lw a4, 12(a0)
; RV32I-NEXT: lw a5, 4(a0)
; RV32I-NEXT: lw a6, 8(a0)
; RV32I-NEXT: lui a7, 1048560
; RV32I-NEXT: slli t0, a4, 1
; RV32I-NEXT: or a1, a3, a5
; RV32I-NEXT: or a2, a6, a4
; RV32I-NEXT: sltiu a0, a3, 0
; RV32I-NEXT: sltu a3, a5, a5
; RV32I-NEXT: seqz t1, a5
; RV32I-NEXT: and t1, t1, a0
; RV32I-NEXT: or a3, a3, t1
; RV32I-NEXT: seqz t1, a6
; RV32I-NEXT: and t1, t1, a3
; RV32I-NEXT: sub a3, a6, a3
; RV32I-NEXT: sltu t2, a6, a6
; RV32I-NEXT: srli t0, t0, 1
; RV32I-NEXT: sub a5, a5, a0
; RV32I-NEXT: xor a6, a4, t0
; RV32I-NEXT: or a4, t2, t1
; RV32I-NEXT: add a7, t0, a7
; RV32I-NEXT: beqz a5, .LBB29_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltiu a0, a5, 0
; RV32I-NEXT: .LBB29_2:
; RV32I-NEXT: mv a6, a6
; RV32I-NEXT: or a5, a1, a2
; RV32I-NEXT: sub a1, a7, a4
; RV32I-NEXT: lui a2, 524256
; RV32I-NEXT: beqz a3, .LBB29_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: sltiu a0, a3, 0
; RV32I-NEXT: .LBB29_4:
; RV32I-NEXT: snez a4, a6
; RV32I-NEXT: seqz a3, a5
; RV32I-NEXT: beq a1, a2, .LBB29_6
; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: sltu a0, a1, a2
; RV32I-NEXT: .LBB29_6:
; RV32I-NEXT: xori a1, a4, 1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: isinf_or_zero_q_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a2, a1, 1
; RV64I-NEXT: or a5, a0, a1
; RV64I-NEXT: li a3, 1
; RV64I-NEXT: sltiu a0, a0, 0
; RV64I-NEXT: srli a2, a2, 1
; RV64I-NEXT: slli a3, a3, 48
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: sub a2, a2, a3
; RV64I-NEXT: lui a3, 16383
; RV64I-NEXT: slli a3, a3, 37
; RV64I-NEXT: mv a1, a1
; RV64I-NEXT: sub a4, a2, a0
; RV64I-NEXT: snez a2, a1
; RV64I-NEXT: seqz a1, a5
; RV64I-NEXT: beq a4, a3, .LBB29_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sltu a0, a4, a3
; RV64I-NEXT: .LBB29_2:
; RV64I-NEXT: xori a2, a2, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 320) ; positive zero or inf.
ret i1 %1
}
define double @tan_f64(double %a) nounwind {
; RV32IFD-LABEL: tan_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call tan
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: tan_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call tan
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: tan_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call tan
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: tan_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call tan
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.tan.f64(double %a)
ret double %1
}
define double @ldexp_double(double %x, i32 %y) nounwind {
; RV32IFD-LABEL: ldexp_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call ldexp
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: ldexp_double:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: sext.w a0, a0
; RV64IFD-NEXT: call ldexp
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: ldexp_double:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call ldexp
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: ldexp_double:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call ldexp
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%z = call double @llvm.ldexp.f64.i32(double %x, i32 %y)
ret double %z
}
define double @asin_f64(double %a) nounwind {
; RV32IFD-LABEL: asin_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call asin
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: asin_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call asin
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: asin_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call asin
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: asin_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call asin
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.asin.f64(double %a)
ret double %1
}
define double @acos_f64(double %a) nounwind {
; RV32IFD-LABEL: acos_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call acos
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: acos_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call acos
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: acos_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call acos
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: acos_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call acos
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.acos.f64(double %a)
ret double %1
}
define double @atan_f64(double %a) nounwind {
; RV32IFD-LABEL: atan_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call atan
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: atan_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call atan
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: atan_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call atan
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: atan_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call atan
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.atan.f64(double %a)
ret double %1
}
define double @atan2_f64(double %a, double %b) nounwind {
; RV32IFD-LABEL: atan2_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call atan2
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: atan2_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call atan2
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: atan2_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call atan2
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: atan2_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call atan2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.atan2.f64(double %a, double %b)
ret double %1
}
define double @sinh_f64(double %a) nounwind {
; RV32IFD-LABEL: sinh_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call sinh
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: sinh_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call sinh
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: sinh_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call sinh
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: sinh_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call sinh
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.sinh.f64(double %a)
ret double %1
}
define double @cosh_f64(double %a) nounwind {
; RV32IFD-LABEL: cosh_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call cosh
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: cosh_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call cosh
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: cosh_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call cosh
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: cosh_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call cosh
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.cosh.f64(double %a)
ret double %1
}
define double @tanh_f64(double %a) nounwind {
; RV32IFD-LABEL: tanh_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call tanh
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: tanh_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call tanh
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: tanh_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call tanh
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: tanh_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call tanh
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.tanh.f64(double %a)
ret double %1
}
define { double, double } @test_modf_f64(double %a) nounwind {
; RV32IFD-LABEL: test_modf_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: mv a0, sp
; RV32IFD-NEXT: call modf
; RV32IFD-NEXT: fld fa1, 0(sp)
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_modf_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call modf
; RV64IFD-NEXT: fld fa1, 0(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: test_modf_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, sp
; RV32I-NEXT: call modf
; RV32I-NEXT: lw a2, 0(sp)
; RV32I-NEXT: lw a3, 4(sp)
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: sw a1, 4(s0)
; RV32I-NEXT: sw a2, 8(s0)
; RV32I-NEXT: sw a3, 12(s0)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_modf_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: call modf
; RV64I-NEXT: ld a1, 0(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%result = call { double, double } @llvm.modf.f64(double %a)
ret { double, double } %result
}
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