TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -mattr=+a,+zacas,+zabha -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV64IA-ZABHA

---
name:            cmpxchg_i8
legalized:       true
regBankSelected: true

body:             |
  bb.0:
    liveins: $x10

    ; RV64IA-ZABHA-LABEL: name: cmpxchg_i8
    ; RV64IA-ZABHA: liveins: $x10
    ; RV64IA-ZABHA-NEXT: {{  $}}
    ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
    ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; RV64IA-ZABHA-NEXT: [[AMOCAS_B:%[0-9]+]]:gpr = AMOCAS_B [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s8))
    ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_B]]
    ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
    %0:gpr(p0) = COPY $x10
    %1:gpr(s64) = G_CONSTANT i64 0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s8))
    $x10 = COPY %3(s64)
    PseudoRET implicit $x10
...
---
name:            cmpxchg_i16
legalized:       true
regBankSelected: true

body:             |
  bb.0:
    liveins: $x10

    ; RV64IA-ZABHA-LABEL: name: cmpxchg_i16
    ; RV64IA-ZABHA: liveins: $x10
    ; RV64IA-ZABHA-NEXT: {{  $}}
    ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
    ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; RV64IA-ZABHA-NEXT: [[AMOCAS_H:%[0-9]+]]:gpr = AMOCAS_H [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s16))
    ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_H]]
    ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
    %0:gpr(p0) = COPY $x10
    %1:gpr(s64) = G_CONSTANT i64 0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s16))
    $x10 = COPY %3(s64)
    PseudoRET implicit $x10
...
---
name:            cmpxchg_i32
legalized:       true
regBankSelected: true

body:             |
  bb.0:
    liveins: $x10

    ; RV64IA-ZABHA-LABEL: name: cmpxchg_i32
    ; RV64IA-ZABHA: liveins: $x10
    ; RV64IA-ZABHA-NEXT: {{  $}}
    ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
    ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; RV64IA-ZABHA-NEXT: [[AMOCAS_W:%[0-9]+]]:gpr = AMOCAS_W [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s32))
    ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_W]]
    ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
    %0:gpr(p0) = COPY $x10
    %1:gpr(s64) = G_CONSTANT i64 0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s32))
    $x10 = COPY %3(s64)
    PseudoRET implicit $x10
...
---
name:            cmpxchg_i64
legalized:       true
regBankSelected: true

body:             |
  bb.0:
    liveins: $x10

    ; RV64IA-ZABHA-LABEL: name: cmpxchg_i64
    ; RV64IA-ZABHA: liveins: $x10
    ; RV64IA-ZABHA-NEXT: {{  $}}
    ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
    ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64))
    ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]]
    ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
    %0:gpr(p0) = COPY $x10
    %1:gpr(s64) = G_CONSTANT i64 0
    %2:gpr(s64) = G_CONSTANT i64 1
    %3:gpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic (s64))
    $x10 = COPY %3(s64)
    PseudoRET implicit $x10
...
---
name:            cmpxchg_with_success_i64
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $x10

    ; RV64IA-ZABHA-LABEL: name: cmpxchg_with_success_i64
    ; RV64IA-ZABHA: liveins: $x10
    ; RV64IA-ZABHA-NEXT: {{  $}}
    ; RV64IA-ZABHA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; RV64IA-ZABHA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
    ; RV64IA-ZABHA-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; RV64IA-ZABHA-NEXT: [[AMOCAS_D_RV64_:%[0-9]+]]:gpr = AMOCAS_D_RV64 [[COPY1]], [[ADDI]], [[COPY]] :: (load store monotonic (s64))
    ; RV64IA-ZABHA-NEXT: [[SLTIU:%[0-9]+]]:gpr = SLTIU [[AMOCAS_D_RV64_]], 1
    ; RV64IA-ZABHA-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    ; RV64IA-ZABHA-NEXT: $x10 = COPY [[AMOCAS_D_RV64_]]
    ; RV64IA-ZABHA-NEXT: $x11 = COPY [[SLTIU]]
    ; RV64IA-ZABHA-NEXT: PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
    ; RV64IA-ZABHA-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    ; RV64IA-ZABHA-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
    ; RV64IA-ZABHA-NEXT: $x10 = COPY [[COPY2]]
    ; RV64IA-ZABHA-NEXT: PseudoRET implicit $x10
    %0:gprb(p0) = COPY $x10
    %1:gprb(s64) = G_CONSTANT i64 0
    %2:gprb(s64) = G_CONSTANT i64 1
    %3:gprb(s64) = G_ATOMIC_CMPXCHG %0(p0), %1, %2 :: (load store monotonic (s64))
    %4:gprb(s64) = G_ICMP intpred(eq), %3(s64), %1
    %5:gprb(s64) = COPY %3(s64)
    %6:gprb(s64) = COPY %4(s64)
    ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
    $x10 = COPY %5(s64)
    $x11 = COPY %6(s64)
    PseudoCALL target-flags(riscv-call) &__muldi3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
    ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
    %7:gprb(s64) = COPY $x10
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...