TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv64.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -verify-machineinstrs %s -o - | \
# RUN: FileCheck %s

---
name:            is_fpclass_f32
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_f

    ; CHECK-LABEL: name: is_fpclass_f32
    ; CHECK: liveins: $f10_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 152
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s32) = COPY $f10_f
    %3:gprb(s64) = G_CONSTANT i64 152
    %4:gprb(s64) = G_CONSTANT i64 0
    %5:gprb(s64) = G_FCLASS %0(s32)
    %6:gprb(s64) = G_AND %5, %3
    %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f32_onehot
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_f

    ; CHECK-LABEL: name: is_fpclass_f32_onehot
    ; CHECK: liveins: $f10_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 256
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s32) = COPY $f10_f
    %3:gprb(s64) = G_CONSTANT i64 256
    %4:gprb(s64) = G_CONSTANT i64 0
    %5:gprb(s64) = G_FCLASS %0(s32)
    %6:gprb(s64) = G_AND %5, %3
    %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f32_one
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_f

    ; CHECK-LABEL: name: is_fpclass_f32_one
    ; CHECK: liveins: $f10_f
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
    ; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 1
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s32) = COPY $f10_f
    %3:gprb(s64) = G_CONSTANT i64 1
    %4:gprb(s64) = G_CONSTANT i64 0
    %5:gprb(s64) = G_FCLASS %0(s32)
    %6:gprb(s64) = G_AND %5, %3
    %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f64
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_d

    ; CHECK-LABEL: name: is_fpclass_f64
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 152
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s64) = COPY $f10_d
    %3:gprb(s64) = G_CONSTANT i64 152
    %4:gprb(s64) = G_CONSTANT i64 0
    %5:gprb(s64) = G_FCLASS %0(s64)
    %6:gprb(s64) = G_AND %5, %3
    %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f64_onehot
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_d

    ; CHECK-LABEL: name: is_fpclass_f64_onehot
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 256
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s64) = COPY $f10_d
    %3:gprb(s64) = G_CONSTANT i64 256
    %4:gprb(s64) = G_CONSTANT i64 0
    %5:gprb(s64) = G_FCLASS %0(s64)
    %6:gprb(s64) = G_AND %5, %3
    %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f64_one
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_d

    ; CHECK-LABEL: name: is_fpclass_f64_one
    ; CHECK: liveins: $f10_d
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
    ; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 1
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s64) = COPY $f10_d
    %3:gprb(s64) = G_CONSTANT i64 1
    %4:gprb(s64) = G_CONSTANT i64 0
    %5:gprb(s64) = G_FCLASS %0(s64)
    %6:gprb(s64) = G_AND %5, %3
    %7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
    $x10 = COPY %7(s64)
    PseudoRET implicit $x10
...