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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=riscv32 -mattr=+f,+zfh < %s \
; RUN: | FileCheck %s --check-prefix=RV32F
; RUN: llc -global-isel -mtriple=riscv32 -mattr=+d,+zfh < %s \
; RUN: | FileCheck %s --check-prefix=RV32D
; RUN: llc -global-isel -mtriple=riscv64 -mattr=+f,+zfh < %s \
; RUN: | FileCheck %s --check-prefix=RV64F
; RUN: llc -global-isel -mtriple=riscv64 -mattr=+d,+zfh < %s \
; RUN: | FileCheck %s --check-prefix=RV64D
define void @zero_f16(ptr %i) {
; RV32F-LABEL: zero_f16:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: sh zero, 0(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_f16:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: sh zero, 0(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_f16:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sh zero, 0(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_f16:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sh zero, 0(a0)
; RV64D-NEXT: ret
entry:
store half 0.0, ptr %i, align 4
ret void
}
define void @zero_bf16(ptr %i) {
; RV32F-LABEL: zero_bf16:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: sh zero, 0(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_bf16:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: sh zero, 0(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_bf16:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sh zero, 0(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_bf16:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sh zero, 0(a0)
; RV64D-NEXT: ret
entry:
store bfloat 0.0, ptr %i, align 4
ret void
}
define void @zero_f32(ptr %i) {
; RV32F-LABEL: zero_f32:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: sw zero, 0(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_f32:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: sw zero, 0(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_f32:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sw zero, 0(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_f32:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sw zero, 0(a0)
; RV64D-NEXT: ret
entry:
store float 0.0, ptr %i, align 4
ret void
}
define void @zero_f64(ptr %i) {
; RV32F-LABEL: zero_f64:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: lui a1, %hi(.LCPI3_0)
; RV32F-NEXT: addi a1, a1, %lo(.LCPI3_0)
; RV32F-NEXT: lw a2, 0(a1)
; RV32F-NEXT: lw a1, 4(a1)
; RV32F-NEXT: sw a2, 0(a0)
; RV32F-NEXT: sw a1, 4(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_f64:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: fcvt.d.w fa5, zero
; RV32D-NEXT: fsd fa5, 0(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_f64:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sd zero, 0(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_f64:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sd zero, 0(a0)
; RV64D-NEXT: ret
entry:
store double 0.0, ptr %i, align 8
ret void
}
define void @zero_v1f32(ptr %i) {
; RV32F-LABEL: zero_v1f32:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: sw zero, 0(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_v1f32:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: sw zero, 0(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_v1f32:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sw zero, 0(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_v1f32:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sw zero, 0(a0)
; RV64D-NEXT: ret
entry:
store <1 x float> <float 0.0>, ptr %i, align 8
ret void
}
define void @zero_v2f32(ptr %i) {
; RV32F-LABEL: zero_v2f32:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: sw zero, 0(a0)
; RV32F-NEXT: sw zero, 4(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_v2f32:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: sw zero, 0(a0)
; RV32D-NEXT: sw zero, 4(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_v2f32:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sw zero, 0(a0)
; RV64F-NEXT: sw zero, 4(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_v2f32:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sw zero, 0(a0)
; RV64D-NEXT: sw zero, 4(a0)
; RV64D-NEXT: ret
entry:
store <2 x float> <float 0.0, float 0.0>, ptr %i, align 8
ret void
}
define void @zero_v4f32(ptr %i) {
; RV32F-LABEL: zero_v4f32:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: sw zero, 0(a0)
; RV32F-NEXT: sw zero, 4(a0)
; RV32F-NEXT: sw zero, 8(a0)
; RV32F-NEXT: sw zero, 12(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_v4f32:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: sw zero, 0(a0)
; RV32D-NEXT: sw zero, 4(a0)
; RV32D-NEXT: sw zero, 8(a0)
; RV32D-NEXT: sw zero, 12(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_v4f32:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sw zero, 0(a0)
; RV64F-NEXT: sw zero, 4(a0)
; RV64F-NEXT: sw zero, 8(a0)
; RV64F-NEXT: sw zero, 12(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_v4f32:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sw zero, 0(a0)
; RV64D-NEXT: sw zero, 4(a0)
; RV64D-NEXT: sw zero, 8(a0)
; RV64D-NEXT: sw zero, 12(a0)
; RV64D-NEXT: ret
entry:
store <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, ptr %i, align 8
ret void
}
define void @zero_v1f64(ptr %i) {
; RV32F-LABEL: zero_v1f64:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: lui a1, %hi(.LCPI7_0)
; RV32F-NEXT: addi a1, a1, %lo(.LCPI7_0)
; RV32F-NEXT: lw a2, 0(a1)
; RV32F-NEXT: lw a1, 4(a1)
; RV32F-NEXT: sw a2, 0(a0)
; RV32F-NEXT: sw a1, 4(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_v1f64:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: fcvt.d.w fa5, zero
; RV32D-NEXT: fsd fa5, 0(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_v1f64:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sd zero, 0(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_v1f64:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sd zero, 0(a0)
; RV64D-NEXT: ret
entry:
store <1 x double> <double 0.0>, ptr %i, align 8
ret void
}
define void @zero_v2f64(ptr %i) {
; RV32F-LABEL: zero_v2f64:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: lui a1, %hi(.LCPI8_0)
; RV32F-NEXT: addi a1, a1, %lo(.LCPI8_0)
; RV32F-NEXT: lw a2, 0(a1)
; RV32F-NEXT: lw a1, 4(a1)
; RV32F-NEXT: sw a2, 0(a0)
; RV32F-NEXT: sw a1, 4(a0)
; RV32F-NEXT: sw a2, 8(a0)
; RV32F-NEXT: sw a1, 12(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_v2f64:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: fcvt.d.w fa5, zero
; RV32D-NEXT: fsd fa5, 0(a0)
; RV32D-NEXT: fsd fa5, 8(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_v2f64:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sd zero, 0(a0)
; RV64F-NEXT: sd zero, 8(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_v2f64:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sd zero, 0(a0)
; RV64D-NEXT: sd zero, 8(a0)
; RV64D-NEXT: ret
entry:
store <2 x double> <double 0.0, double 0.0>, ptr %i, align 8
ret void
}
define void @zero_v4f64(ptr %i) {
; RV32F-LABEL: zero_v4f64:
; RV32F: # %bb.0: # %entry
; RV32F-NEXT: lui a1, %hi(.LCPI9_0)
; RV32F-NEXT: addi a1, a1, %lo(.LCPI9_0)
; RV32F-NEXT: lw a2, 0(a1)
; RV32F-NEXT: lw a1, 4(a1)
; RV32F-NEXT: sw a2, 0(a0)
; RV32F-NEXT: sw a1, 4(a0)
; RV32F-NEXT: sw a2, 8(a0)
; RV32F-NEXT: sw a1, 12(a0)
; RV32F-NEXT: sw a2, 16(a0)
; RV32F-NEXT: sw a1, 20(a0)
; RV32F-NEXT: sw a2, 24(a0)
; RV32F-NEXT: sw a1, 28(a0)
; RV32F-NEXT: ret
;
; RV32D-LABEL: zero_v4f64:
; RV32D: # %bb.0: # %entry
; RV32D-NEXT: fcvt.d.w fa5, zero
; RV32D-NEXT: fsd fa5, 0(a0)
; RV32D-NEXT: fsd fa5, 8(a0)
; RV32D-NEXT: fsd fa5, 16(a0)
; RV32D-NEXT: fsd fa5, 24(a0)
; RV32D-NEXT: ret
;
; RV64F-LABEL: zero_v4f64:
; RV64F: # %bb.0: # %entry
; RV64F-NEXT: sd zero, 0(a0)
; RV64F-NEXT: sd zero, 8(a0)
; RV64F-NEXT: sd zero, 16(a0)
; RV64F-NEXT: sd zero, 24(a0)
; RV64F-NEXT: ret
;
; RV64D-LABEL: zero_v4f64:
; RV64D: # %bb.0: # %entry
; RV64D-NEXT: sd zero, 0(a0)
; RV64D-NEXT: sd zero, 8(a0)
; RV64D-NEXT: sd zero, 16(a0)
; RV64D-NEXT: sd zero, 24(a0)
; RV64D-NEXT: ret
entry:
store <4 x double> <double 0.0, double 0.0, double 0.0, double 0.0>, ptr %i, align 8
ret void
}
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